Searched refs:m_width (Results 1 – 3 of 3) sorted by relevance
| /freebsd/sys/arm/nvidia/tegra124/ |
| H A D | tegra124_clk_pll.c | 96 uint32_t m_width; member
496 *m = get_masked(val, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); in get_divisors()
508 val = set_masked(val, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); in set_divisors()
709 if (m >= (1 << mnp_bits->m_width)) in pll_set_std()
733 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); in pll_set_std()
827 for (m = 1; m < (1 << mnp_bits->m_width); m++) { in plld2_set_freq()
898 if (m >= (1 << mnp_bits->m_width)) in pllx_set_freq()
920 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); in pllx_set_freq()
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| /freebsd/sys/arm64/nvidia/tegra210/ |
| H A D | tegra210_clk_pll.c | 121 uint32_t m_width; member
689 *m = get_masked(val, mnp_bits->m_shift, mnp_bits->m_width); in get_divisors()
701 val = set_masked(val, m, mnp_bits->m_shift, mnp_bits->m_width); in set_divisors()
907 if (m >= (1 << mnp_bits->m_width)) in pll_set_std()
931 reg = set_masked(reg, m, mnp_bits->m_shift, mnp_bits->m_width); in pll_set_std()
1050 for (m = 1; m < (1 << mnp_bits->m_width); m++) { in plld2_set_freq()
1136 if (m >= (1 << mnp_bits->m_width)) in pllx_set_freq()
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| /freebsd/contrib/bsnmp/tests/ |
| H A D | catch.hpp | 8409 size_t m_width = CATCH_CLARA_TEXTFLOW_CONFIG_CONSOLE_WIDTH; member in Catch::clara::TextFlow::Column
8445 auto width = m_column.m_width - indent(); in calcLength()
8488 assert(m_column.m_width > m_column.m_indent); in iterator()
8489 …assert(m_column.m_initialIndent == std::string::npos || m_column.m_width > m_column.m_initialInden… in iterator()
8539 m_width = newWidth; in width()
8551 auto width() const -> size_t { return m_width; } in width()
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