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Searched refs:lo16 (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/JITLink/
H A Dppc64.h219 inline static uint16_t lo16(uint64_t x) { return x & 0xffff; } lo16() function
/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DLoongArch.cpp607 uint32_t lo16 = extractBits(val, 17, 2); in relocate() local
609 write32le(loc + 4, setK16(read32le(loc + 4), lo16)); in relocate()
/freebsd/sys/dev/isp/
H A Disp_library.c983 ISP_IOXGET_16(isp, &src->plogx_ioparm[i].lo16, dst->plogx_ioparm[i].lo16); in isp_get_plogx()
1001 ISP_IOXPUT_16(isp, src->plogx_ioparm[i].lo16, &dst->plogx_ioparm[i].lo16); in isp_put_plogx()
H A Dispmbox.h988 uint16_t lo16; member
H A Disp.c1436 sst = pl.plogx_ioparm[0].lo16 | (pl.plogx_ioparm[0].hi16 << 16); in isp_plogx()
1437 parm1 = pl.plogx_ioparm[1].lo16 | (pl.plogx_ioparm[1].hi16 << 16); in isp_plogx()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td15 def lo16 : SubRegIndex<16, 0>;
23 def sub#Index#_lo16 : ComposedSubRegIndex<!cast<SubRegIndex>(sub#Index), lo16>;
169 let SubRegIndices = [lo16, hi16];
H A DSIRegisterInfo.cpp327 (getSubRegIndexLaneMask(AMDGPU::lo16) | in SIRegisterInfo()
3215 if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::lo16, &RC)) in get32BitRegister()
H A DSIInstrInfo.cpp811 MCRegister SubReg = RI.getSubReg(RegToFix, AMDGPU::lo16); in copyPhysReg()
3438 case AMDGPU::lo16: in foldImmediate()
3476 if (DstReg.isVirtual() && UseMI.getOperand(0).getSubReg() != AMDGPU::lo16) in foldImmediate()
7424 NewInstr.addReg(Src.getReg(), 0, AMDGPU::lo16); in moveToVALUImpl()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td529 // M0 = {hi16:address, lo16:waveID}. Allow passing M0 as a pointer, so that
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp2934 SubReg = AMDGPU::lo16; in ParseRegularReg()