Searched refs:lane1 (Results 1 – 9 of 9) sorted by relevance
25 Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
264 uint32_t lane1; member274 uint32_t lane1; member
1022 pcie_port->regs->axi.status.lane[1] = ®s->axi.status.lane1; in al_pcie_port_handle_init()1089 pcie_port->regs->axi.status.lane[1] = ®s->axi.status.lane1; in al_pcie_port_handle_init()1170 pcie_port->regs->axi.status.lane[1] = ®s->axi.status.lane1; in al_pcie_port_handle_init()
64 analogix,lane1-swing = /bits/ 8 <0x70 0x30>;
379 /* 2. M.2 socket, CON14: pcie30phy port0 lane1, @fe170000 */391 /* 4. M.2 socket, CON16: pcie30phy port1 lane1, @fe180000 */
104 /* bifurcation; lane1 when using 1+1 */
188 phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
521 phy-names = "cp1-pcie0-x2-lane0-phy", "cp1-pcie0-x2-lane1-phy";
723 reset-names = "lane1";