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Searched refs:lane (Results 1 – 25 of 211) sorted by relevance

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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_serdes_25g.c281 enum al_serdes_lane lane, in al_serdes_25g_bist_rx_enable() argument
285 switch (lane) { in al_serdes_25g_bist_rx_enable()
320 al_err("%s: Wrong serdes lane %d\n", __func__, lane); in al_serdes_25g_bist_rx_enable()
326 (enum al_serdes_reg_page)lane, in al_serdes_25g_bist_rx_enable()
333 (enum al_serdes_reg_page)lane, in al_serdes_25g_bist_rx_enable()
340 (enum al_serdes_reg_page)lane, in al_serdes_25g_bist_rx_enable()
349 (enum al_serdes_reg_page)lane, in al_serdes_25g_bist_rx_enable()
357 (enum al_serdes_reg_page)lane, in al_serdes_25g_bist_rx_enable()
368 (enum al_serdes_reg_page)lane, in al_serdes_25g_bist_rx_enable()
382 enum al_serdes_lane lane; in al_serdes_25g_bist_pattern_select() local
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H A Dal_hal_serdes_hssp.c115 enum al_serdes_lane lane);
128 enum al_serdes_lane lane);
508 enum al_serdes_lane lane) in al_serdes_lane_rx_rate_change_sw_flow_en() argument
510 al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 201, 0xfc); in al_serdes_lane_rx_rate_change_sw_flow_en()
511 al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 202, 0xff); in al_serdes_lane_rx_rate_change_sw_flow_en()
512 al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 203, 0xff); in al_serdes_lane_rx_rate_change_sw_flow_en()
513 al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 204, 0xff); in al_serdes_lane_rx_rate_change_sw_flow_en()
514 al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 205, 0x7f); in al_serdes_lane_rx_rate_change_sw_flow_en()
515 al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 205, 0xff); in al_serdes_lane_rx_rate_change_sw_flow_en()
522 enum al_serdes_lane lane) in al_serdes_lane_rx_rate_change_sw_flow_dis() argument
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/freebsd/sys/dev/drm2/
H A Ddrm_dp_helper.c43 int lane) in dp_get_lane_status() argument
45 int i = DP_LANE0_1_STATUS + (lane >> 1); in dp_get_lane_status()
46 int s = (lane & 1) * 4; in dp_get_lane_status()
56 int lane; in drm_dp_channel_eq_ok() local
62 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
63 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_channel_eq_ok()
74 int lane; in drm_dp_clock_recovery_ok() local
77 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
78 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_clock_recovery_ok()
87 int lane) in drm_dp_get_adjust_request_voltage() argument
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/freebsd/sys/arm64/rockchip/
H A Drk_typec_phy.c84 #define TX_TXCC_MGNFS_MULT_000(lane) ((0x4050 | ((lane) << 9)) << 2) argument
85 #define XCVR_DIAG_BIDI_CTRL(lane) ((0x40e8 | ((lane) << 9)) << 2) argument
86 #define XCVR_DIAG_LANE_FCM_EN_MGN(lane) ((0x40f2 | ((lane) << 9)) << 2) argument
87 #define TX_PSC_A0(lane) ((0x4100 | ((lane) << 9)) << 2) argument
88 #define TX_PSC_A1(lane) ((0x4101 | ((lane) << 9)) << 2) argument
89 #define TX_PSC_A2(lane) ((0x4102 | ((lane) << 9)) << 2) argument
90 #define TX_PSC_A3(lane) ((0x4103 | ((lane) << 9)) << 2) argument
91 #define TX_RCVDET_EN_TMR(lane) ((0x4122 | ((lane) << 9)) << 2) argument
92 #define TX_RCVDET_ST_TMR(lane) ((0x4123 | ((lane) << 9)) << 2) argument
94 #define RX_PSC_A0(lane) ((0x8000 | ((lane) << 9)) << 2) argument
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H A Drk3568_pciephy.c87 rk3568_pciephy_bifurcate(device_t dev, int control, uint32_t lane) in rk3568_pciephy_bifurcate() argument
91 switch (lane) { in rk3568_pciephy_bifurcate()
104 device_printf(dev, "Illegal lane %d\n", lane); in rk3568_pciephy_bifurcate()
108 device_printf(dev, "lane %d @ pcie3x%d\n", lane, in rk3568_pciephy_bifurcate()
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_xusbpadctl.c216 struct padctl_lane *lane; member
253 struct padctl_lane *lane);
255 struct padctl_lane *lane);
262 static int usb2_powerup(struct padctl_softc *sc, struct padctl_lane *lane);
263 static int usb2_powerdown(struct padctl_softc *sc, struct padctl_lane *lane);
264 static int pcie_powerup(struct padctl_softc *sc, struct padctl_lane *lane);
265 static int pcie_powerdown(struct padctl_softc *sc, struct padctl_lane *lane);
266 static int sata_powerup(struct padctl_softc *sc, struct padctl_lane *lane);
267 static int sata_powerdown(struct padctl_softc *sc, struct padctl_lane *lane);
358 struct padctl_lane *lane);
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/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_xusbpadctl.c378 struct padctl_lane *lane; member
416 struct padctl_lane *lane);
418 struct padctl_lane *lane);
427 static int usb2_enable(struct padctl_softc *sc, struct padctl_lane *lane);
428 static int usb2_disable(struct padctl_softc *sc, struct padctl_lane *lane);
429 static int hsic_enable(struct padctl_softc *sc, struct padctl_lane *lane);
430 static int hsic_disable(struct padctl_softc *sc, struct padctl_lane *lane);
431 static int pcie_enable(struct padctl_softc *sc, struct padctl_lane *lane);
432 static int pcie_disable(struct padctl_softc *sc, struct padctl_lane *lane);
433 static int sata_enable(struct padctl_softc *sc, struct padctl_lane *lane);
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/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_kr.h160 enum al_eth_an_lt_lane lane,
173 enum al_eth_an_lt_lane lane,
186 enum al_eth_an_lt_lane lane,
199 enum al_eth_an_lt_lane lane,
211 enum al_eth_an_lt_lane lane);
222 enum al_eth_an_lt_lane lane);
232 enum al_eth_an_lt_lane lane);
243 enum al_eth_an_lt_lane lane);
269 enum al_eth_an_lt_lane lane,
332 enum al_eth_an_lt_lane lane);
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H A Dal_hal_eth_kr.c212 enum al_eth_an_lt_lane lane) in al_eth_an_lt_reg_read() argument
218 al_assert(lane == AL_ETH_AN__LT_LANE_0); in al_eth_an_lt_reg_read()
233 switch (lane) { in al_eth_an_lt_reg_read()
275 al_err("%s: Unknown Lane %d\n", __func__, lane); in al_eth_an_lt_reg_read()
282 (an_lt == AL_ETH_AN_REGS) ? "AN" : "LT", lane, reg_addr, val); in al_eth_an_lt_reg_read()
291 enum al_eth_an_lt_lane lane, in al_eth_an_lt_reg_write() argument
310 switch (lane) { in al_eth_an_lt_reg_write()
356 al_err("%s: Unknown Lane %d\n", __func__, lane); in al_eth_an_lt_reg_write()
363 (an_lt == AL_ETH_AN_REGS) ? "AN" : "LT", lane, reg_addr, val); in al_eth_an_lt_reg_write()
499 enum al_eth_an_lt_lane lane, in al_eth_lp_coeff_up_get() argument
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/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dst,st-mipid02.txt6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
37 - data-lanes: shall be <1> for Port 1. for Port 0 dual-lane operation shall be
38 <1 2> or <2 1>. For Port 0 single-lane operation shall be <1> or <2>.
40 - lane-polarities: any lane can be inverted or not.
H A Dov2680.txt22 - clock-lanes: should be set to <0> (clock lane on hardware lane 0).
23 - data-lanes: should be set to <1> (one CSI-2 lane supported).
H A Dtc358743.txt16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
23 is half of the bps per lane due to DDR transmission.
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td256 // Register list of one D register, with byte lane subscripting.
266 // ...with half-word lane subscripting.
276 // ...with word lane subscripting.
287 // Register list of two D registers with byte lane subscripting.
297 // ...with half-word lane subscripting.
307 // ...with word lane subscripting.
317 // Register list of two Q registers with half-word lane subscripting.
327 // ...with word lane subscripting.
339 // Register list of three D registers with byte lane subscripting.
349 // ...with half-word lane subscripting.
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-cadence-sierra.txt29 Each group of PHY lanes with a single master lane should be represented as
30 a sub-node. Note that the actual configuration of each lane is determined by
35 - reg: The master lane number. This is the lowest numbered lane
36 in the lane group.
38 master lane of the sub-node.
H A Dphy-armada38x-comphy.txt22 A sub-node is required for each comphy lane provided by the comphy.
26 - reg: comphy lane number.
28 input port to use for a given comphy lane.
/freebsd/sys/dev/al_eth/
H A Dal_init_eth_kr.c107 enum al_serdes_lane lane; member
198 kr_data->lane, in al_eth_lt_coeff_set()
207 kr_data->lane, in al_eth_lt_coeff_set()
232 kr_data->lane); in al_eth_coeff_req_handle()
349 kr_data->lane, in al_eth_kr_lt_transmitter_task_init()
490 kr_data->lane, in al_eth_kr_lt_transmitter_task_run()
789 enum al_serdes_lane lane, in al_eth_an_lt_execute() argument
801 kr_data.lane = lane; in al_eth_an_lt_execute()
810 kr_data.lane, in al_eth_an_lt_execute()
H A Dal_init_eth_lm.c505 lm_context->lane, in al_eth_serdes_static_tx_params_set()
520 lm_context->lane, in al_eth_serdes_static_tx_params_set()
525 lm_context->lane, in al_eth_serdes_static_tx_params_set()
549 lm_context->lane, in al_eth_serdes_static_rx_params_set()
564 lm_context->lane, in al_eth_serdes_static_rx_params_set()
569 lm_context->lane, in al_eth_serdes_static_rx_params_set()
586 lm_context->lane, &rx_params); in al_eth_rx_equal_run()
598 lm_context->lane); in al_eth_rx_equal_run()
612 lm_context->lane, in al_eth_rx_equal_run()
631 lm_context->lane); in al_eth_rx_equal_run()
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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dqcom,camss.txt133 Definition: The physical clock lane index. On 8916
135 clock lane is lane 1. On 8996 the value must
138 D-PHY physical clock lane is labeled as 7.
144 lane number, while the value of an entry
145 indicates physical lane index. Lane swapping
146 is supported. Physical lane indexes for
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dmvebu-pci.txt77 - marvell,pcie-lane: the physical PCIe lane number, for ports having
149 marvell,pcie-lane = <0>;
170 marvell,pcie-lane = <1>;
187 marvell,pcie-lane = <2>;
204 marvell,pcie-lane = <3>;
221 marvell,pcie-lane = <0>;
238 marvell,pcie-lane = <1>;
255 marvell,pcie-lane = <2>;
272 marvell,pcie-lane = <3>;
289 marvell,pcie-lane = <0>;
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/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-xp-mv78460.dtsi134 marvell,pcie-lane = <0>;
162 marvell,pcie-lane = <1>;
190 marvell,pcie-lane = <2>;
218 marvell,pcie-lane = <3>;
246 marvell,pcie-lane = <0>;
274 marvell,pcie-lane = <1>;
302 marvell,pcie-lane = <2>;
330 marvell,pcie-lane = <3>;
358 marvell,pcie-lane = <0>;
386 marvell,pcie-lane = <0>;
H A Darmada-xp-mv78260.dtsi113 marvell,pcie-lane = <0>;
141 marvell,pcie-lane = <1>;
169 marvell,pcie-lane = <2>;
197 marvell,pcie-lane = <3>;
225 marvell,pcie-lane = <0>;
253 marvell,pcie-lane = <1>;
281 marvell,pcie-lane = <2>;
309 marvell,pcie-lane = <3>;
337 marvell,pcie-lane = <0>;
/freebsd/contrib/ofed/opensm/opensm/
H A Dosm_ucast_lash.c177 int dest_switch, int lane) in remove_semipermanent_depend_for_sp() argument
190 v = cdg_vertex_matrix[lane][sw][i_next_switch]; in remove_semipermanent_depend_for_sp()
195 cdg_vertex_matrix[lane][sw][i_next_switch] = NULL; in remove_semipermanent_depend_for_sp()
208 cdg_vertex_matrix[lane][i_next_switch] in remove_semipermanent_depend_for_sp()
328 int lane) in generate_cdg_for_sp() argument
341 if (cdg_vertex_matrix[lane][sw][next_switch] == NULL) { in generate_cdg_for_sp()
348 cdg_vertex_matrix[lane][sw][next_switch] = v; in generate_cdg_for_sp()
350 v = cdg_vertex_matrix[lane][sw][next_switch]; in generate_cdg_for_sp()
390 int dest_switch, int lane) in set_temp_depend_to_permanent_for_sp() argument
401 v = cdg_vertex_matrix[lane][sw][next_switch]; in set_temp_depend_to_permanent_for_sp()
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1028a-qds-13bb.dts7 * Requires a LS1028A QDS board with lane B rework.
8 * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.
H A Dfsl-ls1028a-qds-13bb.dtso7 * Requires a LS1028A QDS board with lane B rework.
8 * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.
/freebsd/sys/riscv/sifive/
H A Dfu740_pci_dw.c196 int error, phy, lane; in fupci_phy_init() local
252 for (lane = 0; lane < FUDW_LANES_PER_PHY; ++lane) in fupci_phy_init()
253 fupci_phy_write(sc, phy, FUDW_MGMT_PHY_LANE(lane), in fupci_phy_init()

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