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Searched refs:isZeroExtended (Results 1 – 6 of 6) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp131 bool isZeroExtended(Register R, MachineRegisterInfo &MRI) { in isZeroExtended() function
169 (isSignExtended(LHS, MRI) || isZeroExtended(LHS, MRI))) in matchAArch64MulConstCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h623 bool isZeroExtended(const unsigned Reg, in isZeroExtended() function
H A DPPCMIPeephole.cpp290 if (TII->isZeroExtended(Reg, MRI)) in getKnownLeadingZeroCount()
H A DPPCInstrInfo.cpp2427 if (isZeroExtended(SrcReg, MRI)) { in optimizeCompareInstr()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp9479 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { in isZeroExtended() function
9621 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
9641 bool isN0ZExt = isZeroExtended(N0, DAG); in LowerMUL()
9642 bool isN1ZExt = isZeroExtended(N1, DAG); in LowerMUL()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp5061 static bool isZeroExtended(SDValue N, SelectionDAG &DAG) { in isZeroExtended() function
5084 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
5222 bool IsN0ZExt = isZeroExtended(N0, DAG); in selectUmullSmull()
5223 bool IsN1ZExt = isZeroExtended(N1, DAG); in selectUmullSmull()
18322 isZeroExtended(N0, DAG))) in performMulCombine()