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Searched refs:isWave64 (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/
H A DAMDGPU.h92 static bool isWave64(const llvm::opt::ArgList &DriverArgs,
H A DAMDGPU.cpp770 bool AMDGPUToolChain::isWave64(const llvm::opt::ArgList &DriverArgs, in isWave64() function in AMDGPUToolChain
887 bool Wave64 = isWave64(DriverArgs, Kind); in addClangTargetOptions()
1015 bool Wave64 = isWave64(DriverArgs, Kind); in getCommonDeviceLibNames()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUWaitSGPRHazards.cpp473 DsNopCount = ST.isWave64() ? WAVE64_NOPS : WAVE32_NOPS; in run()
H A DVOP2Instructions.td312 let WaveSizePredicate = isWave64 in {
386 let WaveSizePredicate = isWave64 in {
1674 let WaveSizePredicate = isWave64;
1702 let WaveSizePredicate = isWave64;
2133 let WaveSizePredicate = isWave64;
2157 let WaveSizePredicate = isWave64;
2181 let WaveSizePredicate = isWave64;
H A DVOPCInstructions.td328 let WaveSizePredicate = isWave64 in {
1238 let WaveSizePredicate = isWave64 in
1323 let WaveSizePredicate = isWave64 in
1646 let WaveSizePredicate = isWave64;
1658 let WaveSizePredicate = isWave64;
1728 let WaveSizePredicate = isWave64;
1742 let WaveSizePredicate = isWave64;
H A DGCNSubtarget.h1645 bool isWave64() const { in isWave64() function
H A DVOP3PInstructions.td1307 let WaveSizePredicate = isWave64 in {
1729 let WaveSizePredicate = isWave64 in {
1772 let WaveSizePredicate = isWave64;
1802 let WaveSizePredicate = isWave64, SubtargetPredicate = isGFX12Plus in {
1908 let WaveSizePredicate = isWave64, DecoderNamespace = "GFX12W64" in {
2095 let WaveSizePredicate = isWave64, DecoderNamespace = "GFX11W64" in {
H A DAMDGPUInstructionSelector.cpp154 STI.isWave64() ? AMDGPU::S_MOV_B64 : AMDGPU::S_MOV_B32; in selectCOPY()
226 STI.isWave64() ? AMDGPU::S_CMP_LG_U64 : AMDGPU::S_CMP_LG_U32; in selectCOPY_SCC_VCC()
252 unsigned Opcode = STI.isWave64() ? AMDGPU::S_MOV_B64 : AMDGPU::S_MOV_B32; in selectCOPY_VCC_SCC()
266 STI.isWave64() ? AMDGPU::S_CSELECT_B64 : AMDGPU::S_CSELECT_B32; in selectCOPY_VCC_SCC()
398 STI.isWave64()); in selectG_AND_OR_XOR()
3048 const bool Is64 = STI.isWave64(); in selectG_BRCOND()
H A DSIInstructions.td241 let WaveSizePredicate = isWave64 in
399 let WaveSizePredicate = isWave64 in {
762 defm SI_CS_CHAIN_TC_W64 : SI_CS_CHAIN_TC<i64, isWave64>;
2322 let WaveSizePredicate = isWave64;
2813 let WaveSizePredicate = isWave64 in {
2850 } // end isWave64
H A DGCNHazardRecognizer.cpp1588 if (!ST.isWave64() || !SIInstrInfo::isVALU(*MI)) in fixVALUPartialForwardingHazard()
2968 if (!ST.isWave64() || !SIInstrInfo::isSALU(*MI)) in fixVALUMaskWriteHazard()
H A DFLATInstructions.td1128 let WaveSizePredicate = isWave64, SubtargetPredicate = isGFX12PlusNot12_50 in {
1873 let WaveSizePredicate = isWave64, OtherPredicates = [isGFX12PlusNot12_50] in {
H A DSOPInstructions.td246 let WaveSizePredicate = isWave64 in {
1979 let WaveSizePredicate = isWave64 in {
H A DSIInstrInfo.td11 def isWave64 : Predicate<"Subtarget->isWave64()">,
H A DSIInstrInfo.cpp2964 const bool FlushSGPRWrites = (ST.isWave64() && ST.hasVALUMaskWriteHazard()) || in insertIndirectBranch()
8087 ST.isWave64() ? AMDGPU::S_CSELECT_B64 : AMDGPU::S_CSELECT_B32; in lowerSelect()
9094 uint64_t IndexStride = ST.isWave64() ? 3 : 2; in getScratchRsrcWords23()
H A DDSInstructions.td831 let WaveSizePredicate = isWave64, SubtargetPredicate = HasGFX950Insts, mayStore = 0 in {
H A DVOP3Instructions.td1457 let WaveSizePredicate = isWave64 in {
H A DSIISelLowering.cpp17537 return Subtarget->isWave64() ? &AMDGPU::SReg_64RegClass in getRegClassFor()