Searched refs:isVerilogBegin (Results 1 – 4 of 4) sorted by relevance
766 (Keywords.isVerilogBegin(*FormatTok) || VerilogHierarchy))) && in parseBlock() 1987 if (Keywords.isVerilogBegin(*FormatTok) || in parseStructuralElement() 2806 return Style.isVerilog() ? Keywords.isVerilogBegin(Tok) in isBlockBegin() 4520 else if (!Style.IndentCaseBlocks && Keywords.isVerilogBegin(*FormatTok)) in parseVerilogCaseLabel()
1856 bool isVerilogBegin(const FormatToken &Tok) const { in isVerilogBegin() function
1250 (Style.isVerilog() && Keywords.isVerilogBegin(*NextNonComment))) { in getNewLineColumn()
1354 Keywords.isVerilogBegin(*Tok->Previous)) { in consumeToken()5583 if (!Keywords.isVerilogBegin(Right) && Keywords.isVerilogEndOfLabel(Left)) in mustBreakBefore()