Searched refs:isVShiftRImm (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 511 bool isVShiftRImm(Register Reg, MachineRegisterInfo &MRI, LLT Ty, in isVShiftRImm() function
531 return isVShiftRImm(MI.getOperand(2).getReg(), MRI, Ty, Imm); in matchVAshrLshrImm()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 6645 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, in isVShiftRImm() function
6686 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) { in LowerShift()
17533 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) { in PerformIntrinsicCombine()
17542 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) in PerformIntrinsicCombine()
17565 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt)) in PerformIntrinsicCombine()
17629 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt)) in PerformIntrinsicCombine()
17783 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) { in PerformShiftCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 14812 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, int64_t &Cnt) { in isVShiftRImm() function
14933 if (isVShiftRImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize) { in LowerVectorSRA_SRL_SHL()
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