Searched refs:isVI (Results 1 – 6 of 6) sorted by relevance
209 bool isVI() const;
113 } else if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. in decodeSMEMOffset()675 if ((isVI() || isGFX9()) && in getInstruction()716 if ((isVI() || isGFX9()) && in getInstruction()2051 bool AMDGPUDisassembler::isVI() const { in isVI() function in AMDGPUDisassembler
2092 if (isVI(STI) || isGFX9(STI)) in getNfmtLookupTable()2347 bool isVI(const MCSubtargetInfo &STI) { in isVI() function2364 return isVI(STI) || isGFX9(STI) || isGFX10(STI); in isGFX8_GFX9_GFX10()2368 return isVI(STI) || isGFX9Plus(STI); in isGFX8Plus()2412 return isSI(STI) || isCI(STI) || isVI(STI) || isGFX9(STI); in isNotGFX10Plus()
1510 bool isVI(const MCSubtargetInfo &STI);
492 assert(!AMDGPU::isVI(STI) || isUInt<20>(Offset)); in getSMEMOffsetEncoding()
1520 bool isVI() const { in isVI() function in __anon6862249c0111::AMDGPUAsmParser1521 return AMDGPU::isVI(getSTI()); in isVI()1588 return !isVI() && !isGFX9(); in hasSGPR102_SGPR103()2244 if (AsmParser->isVI()) in isSDWAOperand()4811 : (isVI() || IsBuffer) ? "expected a 20-bit unsigned offset" in validateSMEMOffset()6622 return (isVI() || isGFX9()) && getTargetStreamer().getTargetID()->isXnackSupported(); in subtargetHasRegister()9647 return isVI() || isGFX9(); in isSupportedDPPCtrl()9987 cvtSDWA(Inst, Operands, SIInstrFlags::VOPC, isVI()); in cvtSdwaVOPC()