| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIShrinkInstructions.cpp | 437 if (Src1.isReg() && TRI->isVGPR(*MRI, Src1.getReg())) in shrinkMadFma()
439 else if (Src0.isReg() && TRI->isVGPR(*MRI, Src0.getReg())) in shrinkMadFma()
474 if (Src2.isReg() && TRI->isVGPR(*MRI, Src2.getReg())) { in shrinkMadFma()
707 if (!TRI->isVGPR(*MRI, X)) in matchSwap()
730 if (!TRI->isVGPR(*MRI, Y)) in matchSwap()
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| H A D | SIRegisterInfo.h | 325 bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
328 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); in isVectorRegister()
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| H A D | SIRegisterInfo.td | 79 class SIReg <string n, bits<8> regIdx = 0, bit isVGPR = 0,
87 let HWEncoding{8} = isVGPR;
115 bit isVGPR = 0, bit isAGPR = 0,
117 def _LO16 : SIReg<n#".l", regIdx, isVGPR, isAGPR>;
118 def _HI16 : SIReg<!if(ArtificialHigh, "", n#".h"), regIdx, isVGPR, isAGPR,
129 let HWEncoding{8} = isVGPR;
161 defm EXEC_LO : SIRegLoHi16<"exec_lo", 126, /*ArtificialHigh=*/1, /*isVGPR=*/0,
307 /*isVGPR=*/0, /*isAGPR=*/0, /*DwarfEncodings=*/
316 /*isVGPR=*/ 1, /*isAGPR=*/ 0, /*DwarfEncodings=*/
324 /*isVGPR=*/ 0, /*isAGPR=*/ 1, /*DwarfEncodings=*/
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| H A D | SIPreAllocateWWMRegs.cpp | 101 if (!TRI->isVGPR(*MRI, Reg)) in processDef()
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| H A D | GCNVOPDUtils.cpp | 126 if (!Src->isReg() || !TRI->isVGPR(MRI, Src->getReg())) in checkVOPDRegConstraints()
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| H A D | SIFoldOperands.cpp | 381 if (TRI->isVGPR(*MRI, DstReg) && TRI->isSGPRReg(*MRI, SrcReg) && in foldCopyToVGPROfScalarAddOfFrameIndex()
862 !TII->getRegisterInfo().isVGPR(*MRI, OtherOp.getReg())) in tryAddToFoldList()
1326 if (Size == 2 && TRI->isVGPR(*MRI, UseMI->getOperand(0).getReg()) && in foldOperand()
2324 if (!ST->hasGFX90AInsts() || !TRI->isVGPR(*MRI, Reg) || in tryFoldRegSequence()
2349 if (!TRI->isVGPR(*MRI, Reg) || !MRI->hasOneNonDBGUse(Reg)) in tryFoldRegSequence()
2471 if (!TRI->isVGPR(*MRI, PhiOut)) in tryFoldPhiAGPR()
2582 if (DefReg.isPhysical() || !TRI->isVGPR(*MRI, DefReg)) in tryFoldLoad()
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| H A D | GCNHazardRecognizer.cpp | 737 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkDPPHazards()
1594 if (Use.isReg() && TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in fixVALUPartialForwardingHazard()
1743 if (Use.isReg() && TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in fixVALUTransUseHazard()
1887 if (!TRI.isVGPR(MRI, AmtReg) || ((AmtReg - AMDGPU::VGPR0) & 7) != 7) in fixShift64HighRegBug()
2090 if (!Use.isReg() || !TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkMAIHazards908()
2500 if (!Op.isReg() || !TRI.isVGPR(MF.getRegInfo(), Op.getReg())) in checkMAILdStHazards()
2554 if (!Op.isReg() || !TRI->isVGPR(MF.getRegInfo(), Op.getReg())) in checkPermlaneHazards()
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| H A D | SIRegisterInfo.cpp | 897 return Src1.isImm() || (Src1.isReg() && TRI.isVGPR(MI.getMF()->getRegInfo(), in isFIPlusImmOrVGPR()
902 return Src0.isImm() || (Src0.isReg() && TRI.isVGPR(MI.getMF()->getRegInfo(), in isFIPlusImmOrVGPR()
1468 bool IsVGPR = TRI->isVGPR(MRI, Reg); in spillVGPRtoAGPR()
1470 if (IsVGPR == TRI->isVGPR(MRI, ValueReg)) { in spillVGPRtoAGPR()
3710 bool SIRegisterInfo::isVGPR(const MachineRegisterInfo &MRI, in isVGPR() function in SIRegisterInfo
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| H A D | SIInstrInfo.cpp | 3576 bool isVGPRCopy = RI.isVGPR(*MRI, DstReg); in foldImmediate()
4572 if (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg())) in canShrink()
4586 if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) || in canShrink()
4597 if (Src1 && (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()) || in canShrink()
6169 if (Src0.isReg() && RI.isVGPR(MRI, Src0.getReg())) { in legalizeOperandsVOP2()
6175 if (Src1.isReg() && RI.isVGPR(MRI, Src1.getReg())) { in legalizeOperandsVOP2()
6195 if (!RI.isVGPR(MRI, MI.getOperand(Src2Idx).getReg())) in legalizeOperandsVOP2()
6208 RI.isVGPR(MRI, Src1.getReg())) { in legalizeOperandsVOP2()
6351 !RI.isVGPR(MRI, MI.getOperand(VOP3Idx[2]).getReg())) in legalizeOperandsVOP3()
7818 RI.isVGPR(MRI, Inst.getOperand(1).getReg())) { in moveToVALUImpl()
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| H A D | SIFixSGPRCopies.cpp | 950 if (TRI->isVGPR(*MRI, Inst->getOperand(0).getReg())) { in analyzeVGPRToSGPRCopy()
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| H A D | SIPeepholeSDWA.cpp | 1360 if (!Op.isImm() && !(Op.isReg() && !TRI->isVGPR(*MRI, Op.getReg()))) in legalizeScalarOperands()
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| H A D | SIInstrInfo.h | 1069 return MO.isReg() && RI.isVGPR(MRI, MO.getReg());}); in hasVGPRUses()
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| H A D | SIWholeQuadMode.cpp | 887 if (TRI->isVGPR(*MRI, Op0.getReg())) { in lowerKillF32()
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| H A D | SIInsertWaitcnts.cpp | 995 if (TRI->isVGPR(*MRI, DefMO.getReg())) { in updateByEvent()
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