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Searched refs:isVGPR (Results 1 – 12 of 12) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIShrinkInstructions.cpp427 if (Src1.isReg() && TRI->isVGPR(*MRI, Src1.getReg())) in shrinkMadFma()
429 else if (Src0.isReg() && TRI->isVGPR(*MRI, Src0.getReg())) in shrinkMadFma()
455 if (Src2.isReg() && TRI->isVGPR(*MRI, Src2.getReg())) { in shrinkMadFma()
673 if (!TRI->isVGPR(*MRI, X)) in matchSwap()
696 if (!TRI->isVGPR(*MRI, Y)) in matchSwap()
H A DSIRegisterInfo.h295 bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
298 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg);
H A DSIPreAllocateWWMRegs.cpp97 if (!TRI->isVGPR(*MRI, Reg)) in processDef()
H A DSIFoldOperands.cpp590 !TII->getRegisterInfo().isVGPR(*MRI, OtherOp.getReg())) in tryAddToFoldList()
987 if (TRI->isAGPR(*MRI, Reg0) && TRI->isVGPR(*MRI, Reg1)) in foldOperand()
989 else if (TRI->isVGPR(*MRI, Reg0) && TRI->isAGPR(*MRI, Reg1)) in foldOperand()
1778 if (!ST->hasGFX90AInsts() || !TRI->isVGPR(*MRI, Reg) || in tryFoldRegSequence()
1803 if (!TRI->isVGPR(*MRI, Reg) || !MRI->hasOneNonDBGUse(Reg)) in tryFoldRegSequence()
1925 if (!TRI->isVGPR(*MRI, PhiOut)) in tryFoldPhiAGPR()
2036 if (DefReg.isPhysical() || !TRI->isVGPR(*MRI, DefReg)) in tryFoldLoad()
H A DGCNHazardRecognizer.cpp754 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkDPPHazards()
1503 if (Use.isReg() && TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in fixVALUPartialForwardingHazard()
1652 if (Use.isReg() && TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in fixVALUTransUseHazard()
1796 if (!TRI.isVGPR(MRI, AmtReg) || ((AmtReg - AMDGPU::VGPR0) & 7) != 7) in fixShift64HighRegBug()
1999 if (!Use.isReg() || !TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkMAIHazards908()
2381 if (!Op.isReg() || !TRI.isVGPR(MF.getRegInfo(), Op.getReg())) in checkMAILdStHazards()
H A DSIInstrInfo.cpp3459 bool isVGPRCopy = RI.isVGPR(*MRI, DstReg); in foldImmediate()
4428 if (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg())) in canShrink()
4441 if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) || in canShrink()
4452 if (Src1 && (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()) || in canShrink()
5871 if (Src0.isReg() && RI.isVGPR(MRI, Src0.getReg())) { in legalizeOperandsVOP2()
5877 if (Src1.isReg() && RI.isVGPR(MRI, Src1.getReg())) { in legalizeOperandsVOP2()
5897 if (!RI.isVGPR(MRI, MI.getOperand(Src2Idx).getReg())) in legalizeOperandsVOP2()
5910 RI.isVGPR(MRI, Src1.getReg())) { in legalizeOperandsVOP2()
6053 !RI.isVGPR(MRI, MI.getOperand(VOP3Idx[2]).getReg())) in legalizeOperandsVOP3()
7375 RI.isVGPR(MRI, Inst.getOperand(1).getReg())) { in moveToVALUImpl()
[all …]
H A DSIRegisterInfo.cpp1232 bool IsVGPR = TRI->isVGPR(MRI, Reg); in spillVGPRtoAGPR()
1234 if (IsVGPR == TRI->isVGPR(MRI, ValueReg)) { in spillVGPRtoAGPR()
3012 bool SIRegisterInfo::isVGPR(const MachineRegisterInfo &MRI, in isVGPR() function in SIRegisterInfo
H A DSIFixSGPRCopies.cpp932 if (TRI->isVGPR(*MRI, Inst->getOperand(0).getReg())) { in analyzeVGPRToSGPRCopy()
H A DSIPeepholeSDWA.cpp1212 if (!Op.isImm() && !(Op.isReg() && !TRI->isVGPR(*MRI, Op.getReg()))) in legalizeScalarOperands()
H A DSIInstrInfo.h1024 return MO.isReg() && RI.isVGPR(MRI, MO.getReg());}); in hasVGPRUses()
H A DSIWholeQuadMode.cpp875 if (TRI->isVGPR(*MRI, Op0.getReg())) { in lowerKillF32()
H A DSIInsertWaitcnts.cpp889 TRI->isVGPR(*MRI, DefMO.getReg())) { in updateByEvent()