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Searched refs:isUse (Results 1 – 25 of 118) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineCycleAnalysis.cpp131 if (MO.isUse()) { in isCycleInvariant()
156 if (!MO.isUse()) in isCycleInvariant()
H A DBreakFalseDeps.cpp197 if (!MO.isReg() || !MO.getReg() || !MO.isUse() || !MO.isUndef()) in processDefs()
222 if (MO.isUse()) in processDefs()
H A DMachineInstr.cpp281 if (NewMO->isUse()) { in addOperand()
291 if (NewMO->isUse() && isDebugInstr()) in addOperand()
988 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
1072 if (MO.isReg() && MO.isUse() && MO.getReg() == Reg) in hasRegisterImplicitUseOperand()
1086 if (!MO.isReg() || !MO.isUse()) in findRegisterUseOperandIdx()
1114 if (MO.isUse()) in readsWritesVirtualRegister()
1193 assert(UseMO.isUse() && "UseIdx must be a use operand"); in tieOperands()
1227 if (MO.isUse()) in findTiedOperandIdx()
1232 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) in findTiedOperandIdx()
1295 if (MO.isReg() && MO.isUse()) in clearKillInfo()
[all …]
H A DMachineConvergenceVerifier.cpp54 if (!MO.isReg() || !MO.isUse()) in findAndCheckConvergenceTokenUsed()
H A DLiveIntervals.cpp825 if (MO.isUse()) { in addKillFlags()
901 float LiveIntervals::getSpillWeight(bool isDef, bool isUse, in getSpillWeight() argument
905 return getSpillWeight(isDef, isUse, MBFI, MI.getParent(), PSI); in getSpillWeight()
908 float LiveIntervals::getSpillWeight(bool isDef, bool isUse, in getSpillWeight() argument
912 float Weight = isDef + isUse; in getSpillWeight()
1063 if (MO.isUse()) { in updateAllRanges()
1167 if (MOP.isReg() && MOP.isUse()) in handleMoveDown()
1469 if (MO->isReg() && !MO->isUse()) in handleMoveUp()
1682 } else if (MO.isUse()) { in repairOldRegInRange()
H A DCriticalAntiDepBreaker.cpp215 if (MO.isUse() && Special) { in PrescanInstruction()
315 if (!MO.isUse()) continue; in ScanInstruction()
617 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) { in BreakAntiDependencies()
H A DTwoAddressInstructionPass.cpp350 if (MO.isUse() && DI->second < LastUse) in noUseAfterLastDef()
474 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse()
521 if (MO.isReg() && MO.isUse() && in findOnlyInterestingUse()
1147 if (MO.isUse()) { in rescheduleKillAboveMI()
1186 if (MO.isUse()) { in rescheduleKillAboveMI()
1447 if (MO.isUse()) { in tryInstructionTransform()
1534 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid"); in collectTiedOperands()
1654 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() && in processTiedPairs()
H A DProcessImplicitDefs.cpp114 if (MO.isUse()) in processImplicitDef()
H A DExpandPostRAPseudos.cpp82 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && in LowerSubregToReg()
H A DMachineSink.cpp353 if (MO.isUse()) { in INITIALIZE_PASS_DEPENDENCY()
460 if (Reg.isPhysical() && MO.isUse() && in PerformSinkAndFold()
1317 if (MO.isUse() && !MRI->isConstantPhysReg(Reg) && in isProfitableToSinkTo()
1424 if (MO.isUse()) { in FindSuccToSinkTo()
1436 if (MO.isUse()) in FindSuccToSinkTo()
1813 assert(MO.isReg() && MO.isUse()); in aggressivelySinkIntoCycle()
2225 } else if (MO.isUse()) { in hasRegisterDependency()
H A DLiveIntervalCalc.cpp148 if (MO.isUse()) in extendToUses()
H A DLiveRangeShrink.cpp163 if (MO.isUse()) in runOnMachineFunction()
H A DMachineLoopInfo.cpp255 if (MO.isUse()) { in isLoopInvariant()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp262 if (MO.isUse()) { in delayHasHazard()
318 assert(Reg.isUse() && "CALL first operand is not a use."); in insertCallDefsUses()
325 assert(Operand1.isUse() && "CALLrr second operand is not a use."); in insertCallDefsUses()
345 if (MO.isUse()) { in insertDefsUses()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiDelaySlotFiller.cpp212 if (MO.isUse()) { in delayHasHazard()
238 else if (MO.isUse()) in insertDefsUses()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp235 assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse()); in getPredRegFor()
331 if (MO.isReg() && MO.isUse()) in isScalarPred()
352 if (!MO.isReg() || !MO.isUse()) in convertToPredForm()
H A DHexagonNewValueJump.cpp169 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { in INITIALIZE_PASS_DEPENDENCY()
640 if (!MO.isReg() || !MO.isUse()) in runOnMachineFunction()
647 if (!Op.isReg() || !Op.isUse() || !Op.isKill()) in runOnMachineFunction()
H A DHexagonSubtarget.cpp357 if (MO.isUse() && !MI->isCopy() && in apply()
474 if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) { in adjustSchedDependency()
581 if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) { in restoreLatency()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMIChecking.cpp111 if (!MO.isReg() || MO.isUse()) in hasLiveDefs()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRegUnits.h67 assert(O->isUse() && "Reg operand not a def and not a use"); in accumulateUsedDefed()
H A DMachineRegisterInfo.h1063 if ((!ReturnUses && op->isUse()) || in defusechain_iterator()
1077 if (Op->isUse()) in advance()
1167 if ((!ReturnUses && op->isUse()) || in defusechain_instr_iterator()
1181 if (Op->isUse()) in advance()
H A DLiveIntervals.h121 LLVM_ABI static float getSpillWeight(bool isDef, bool isUse,
128 LLVM_ABI static float getSpillWeight(bool isDef, bool isUse,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVVMV0Elimination.cpp126 assert(MO.isUse() && MO.getSubReg() == RISCV::NoSubRegister && in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLatencyMutations.cpp785 if (OP.isReg() && OP.isUse() && OP.getReg() == RegID && in modifyMixedWidthFP()
791 if (OP.isReg() && OP.isUse() && OP.getReg() == RegID && in modifyMixedWidthFP()
801 if (OP.isReg() && OP.isUse() && OP.getReg() == RegID && in modifyMixedWidthFP()
H A DA15SDOptimizer.cpp191 if ((!MO.isReg()) || (!MO.isUse())) in eraseInstrWithNoUses()
401 if (!MO.isReg() || !MO.isUse()) in getReadDPRs()

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