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Searched refs:isUse (Results 1 – 25 of 116) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineCycleAnalysis.cpp113 if (MO.isUse()) { in isCycleInvariant()
138 if (!MO.isUse()) in isCycleInvariant()
H A DBreakFalseDeps.cpp198 if (!MO.isReg() || !MO.getReg() || !MO.isUse() || !MO.isUndef()) in processDefs()
223 if (MO.isUse()) in processDefs()
H A DMachineInstr.cpp279 if (NewMO->isUse()) { in addOperand()
289 if (NewMO->isUse() && isDebugInstr()) in addOperand()
961 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
1045 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg) in hasRegisterImplicitUseOperand()
1059 if (!MO.isReg() || !MO.isUse()) in findRegisterUseOperandIdx()
1087 if (MO.isUse()) in readsWritesVirtualRegister()
1166 assert(UseMO.isUse() && "UseIdx must be a use operand"); in tieOperands()
1200 if (MO.isUse()) in findTiedOperandIdx()
1205 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) in findTiedOperandIdx()
1268 if (MO.isReg() && MO.isUse()) in clearKillInfo()
[all …]
H A DMachineLoopInfo.cpp268 if (MO.isUse()) { in isLoopInvariant()
290 if (!MO.isUse()) in isLoopInvariant()
H A DMachineConvergenceVerifier.cpp55 if (!MO.isReg() || !MO.isUse()) in findAndCheckConvergenceTokenUsed()
H A DCriticalAntiDepBreaker.cpp214 if (MO.isUse() && Special) { in PrescanInstruction()
312 if (!MO.isUse()) continue; in ScanInstruction()
616 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) { in BreakAntiDependencies()
H A DLiveIntervals.cpp800 if (MO.isUse()) { in addKillFlags()
876 float LiveIntervals::getSpillWeight(bool isDef, bool isUse, in getSpillWeight() argument
879 return getSpillWeight(isDef, isUse, MBFI, MI.getParent()); in getSpillWeight()
882 float LiveIntervals::getSpillWeight(bool isDef, bool isUse, in getSpillWeight() argument
885 return (isDef + isUse) * MBFI->getBlockFreqRelativeToEntryBlock(MBB); in getSpillWeight()
1030 if (MO.isUse()) { in updateAllRanges()
1133 if (MOP.isReg() && MOP.isUse()) in handleMoveDown()
1434 if (MO->isReg() && !MO->isUse()) in handleMoveUp()
1646 } else if (MO.isUse()) { in repairOldRegInRange()
H A DTwoAddressInstructionPass.cpp350 if (MO.isUse() && DI->second < LastUse) in noUseAfterLastDef()
474 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse()
518 if (MO.isReg() && MO.isUse() && in findOnlyInterestingUse()
1145 if (MO.isUse()) { in rescheduleKillAboveMI()
1184 if (MO.isUse()) { in rescheduleKillAboveMI()
1445 if (MO.isUse()) { in tryInstructionTransform()
1532 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid"); in collectTiedOperands()
1652 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() && in processTiedPairs()
H A DProcessImplicitDefs.cpp115 if (MO.isUse()) in processImplicitDef()
H A DExpandPostRAPseudos.cpp63 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && in LowerSubregToReg()
H A DMachineSink.cpp313 if (MO.isUse()) { in INITIALIZE_PASS_DEPENDENCY()
420 if (Reg.isPhysical() && MO.isUse() && in PerformSinkAndFold()
1151 if (MO.isUse() && !MRI->isConstantPhysReg(Reg) && !TII->isIgnorableUse(MO)) in isProfitableToSinkTo()
1254 if (MO.isUse()) { in FindSuccToSinkTo()
1266 if (MO.isUse()) continue; in FindSuccToSinkTo()
2034 } else if (MO.isUse()) { in hasRegisterDependency()
H A DLiveIntervalCalc.cpp149 if (MO.isUse()) in extendToUses()
H A DLiveRangeShrink.cpp145 if (MO.isUse()) in runOnMachineFunction()
H A DInlineSpiller.cpp701 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg()) { in reMaterializeFor()
927 if (MO.isUse() && !MO.readsReg() && !MO.isTied()) in foldMemoryOperand()
959 if (MO.isUse()) in foldMemoryOperand()
987 if (MO->isUse()) in foldMemoryOperand()
1221 if (MO.isUse()) { in spillAroundUses()
H A DRegisterScavenging.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp264 if (MO.isUse()) { in delayHasHazard()
305 assert(Reg.isUse() && "CALL first operand is not a use."); in insertCallDefsUses()
312 assert(Operand1.isUse() && "CALLrr second operand is not a use."); in insertCallDefsUses()
332 if (MO.isUse()) { in insertDefsUses()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiDelaySlotFiller.cpp213 if (MO.isUse()) { in delayHasHazard()
239 else if (MO.isUse()) in insertDefsUses()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenPredicate.cpp258 assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse()); in getPredRegFor()
354 if (MO.isReg() && MO.isUse()) in isScalarPred()
375 if (!MO.isReg() || !MO.isUse()) in convertToPredForm()
H A DHexagonNewValueJump.cpp177 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { in INITIALIZE_PASS_DEPENDENCY()
648 if (!MO.isReg() || !MO.isUse()) in runOnMachineFunction()
655 if (!Op.isReg() || !Op.isUse() || !Op.isKill()) in runOnMachineFunction()
H A DHexagonSubtarget.cpp358 if (MO.isUse() && !MI->isCopy() && in apply()
473 if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) { in adjustSchedDependency()
580 if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) { in restoreLatency()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h1054 if ((!ReturnUses && op->isUse()) || in defusechain_iterator()
1068 if (Op->isUse()) in advance()
1162 if ((!ReturnUses && op->isUse()) || in defusechain_instr_iterator()
1176 if (Op->isUse()) in advance()
H A DLiveIntervals.h116 static float getSpillWeight(bool isDef, bool isUse,
121 static float getSpillWeight(bool isDef, bool isUse,
H A DLiveRegUnits.h66 assert(O->isUse() && "Reg operand not a def and not a use"); in accumulateUsedDefed()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMIChecking.cpp117 if (!MO.isReg() || MO.isUse()) in hasLiveDefs()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp190 if ((!MO.isReg()) || (!MO.isUse())) in eraseInstrWithNoUses()
400 if (!MO.isReg() || !MO.isUse()) in getReadDPRs()

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