| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrFragmentsSIMD.td | 1113 cast<MaskedLoadSDNode>(N)->isUnindexed();
1128 cast<MaskedLoadSDNode>(N)->isUnindexed();
1138 cast<MaskedStoreSDNode>(N)->isUnindexed();
1153 cast<MaskedStoreSDNode>(N)->isUnindexed();
1162 cast<MaskedStoreSDNode>(N)->isUnindexed();
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| H A D | X86ISelLowering.cpp | 51388 assert(ML->isUnindexed() && "Unexpected indexed masked load!"); in reduceMaskedLoadToScalarLoad()
51428 assert(ML->isUnindexed() && "Unexpected indexed masked load!"); in combineMaskedLoadConstantMask()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenDAGPatterns.cpp | 922 if (isUnindexed()) in getPredCode()
938 if (!isUnindexed() && !isNonExtLoad() && !isAnyExtLoad() && in getPredCode()
963 if (!isUnindexed() && !isTruncStore() && !isNonTruncStore() && in getPredCode()
1095 if (isUnindexed()) in getPredCode()
1204 bool TreePredicateFn::isUnindexed() const { in isUnindexed() function in TreePredicateFn
1335 if (isUnindexed()) in getCodeToRunOnSDNode()
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| H A D | CodeGenDAGPatterns.h | 548 bool isUnindexed() const;
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | GlobalISelEmitter.cpp | 106 if (P.isUnindexed()) in explainPredicates()
224 if (Predicate.isUnindexed()) in isTrivialOperatorNode()
665 if (Predicate.isUnindexed()) in addBuiltinPredicates()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGNodes.h | 2421 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2558 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2731 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 2992 assert(cast<LoadSDNode>(Op)->isUnindexed()); in SplitHvxMemOp()
3001 assert(cast<StoreSDNode>(Op)->isUnindexed()); in SplitHvxMemOp()
3011 assert(MaskN->isUnindexed()); in SplitHvxMemOp()
3050 assert(LoadN->isUnindexed() && "Not widening indexed loads yet"); in WidenHvxLoad()
3082 assert(StoreN->isUnindexed() && "Not widening indexed stores yet"); in WidenHvxStore()
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| H A D | HexagonISelLowering.cpp | 3187 if (!LN->isUnindexed()) in LowerUnalignedLoad()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 451 assert(N->isUnindexed() && "Indexed vector load?"); in ScalarizeVecRes_LOAD()
943 assert(N->isUnindexed() && "Indexed store of one-element vector?"); in ScalarizeVecOp_STORE()
2076 assert(LD->isUnindexed() && "Indexed VP load during type legalization!"); in SplitVecRes_VP_LOAD()
2157 assert(SLD->isUnindexed() && in SplitVecRes_VP_STRIDED_LOAD()
2238 assert(MLD->isUnindexed() && "Indexed masked load during type legalization!"); in SplitVecRes_MLOAD()
3621 assert(N->isUnindexed() && "Indexed vp_store of vector?"); in SplitVecOp_VP_STORE()
3701 assert(N->isUnindexed() && "Indexed vp_strided_store of a vector?"); in SplitVecOp_VP_STRIDED_STORE()
3775 assert(N->isUnindexed() && "Indexed masked store of vector?"); in SplitVecOp_MSTORE()
3938 assert(N->isUnindexed() && "Indexed store of vector?"); in SplitVecOp_STORE()
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| H A D | DAGCombiner.cpp | 11970 if (MST->isUnindexed() && MST->isSimple() && MST1->isUnindexed() && in visitMSTORE()
11987 if (ISD::isConstantSplatVectorAllOnes(Mask.getNode()) && MST->isUnindexed() && in visitMSTORE()
11998 if (MST->isTruncatingStore() && MST->isUnindexed() && in visitMSTORE()
12024 MST->isUnindexed() && !MST->isCompressingStore() && in visitMSTORE()
12173 if (ISD::isConstantSplatVectorAllOnes(Mask.getNode()) && MLD->isUnindexed() && in visitMLOAD()
13689 LN00->getExtensionType() != ISD::ZEXTLOAD && LN00->isUnindexed()) { in visitSIGN_EXTEND()
14006 LN00->getExtensionType() != ISD::SEXTLOAD && LN00->isUnindexed()) { in visitZERO_EXTEND()
19123 if (OptLevel != CodeGenOptLevel::None && LD->isUnindexed() && in visitLOAD()
19139 if (LD->isUnindexed()) { in visitLOAD()
21431 ST->isUnindexed()) { in visitSTORE()
[all …]
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| H A D | TargetLowering.cpp | 4657 if (Lod->isSimple() && Lod->isUnindexed() && in SimplifySetCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 10137 assert(LD->isUnindexed() && "Expected a unindexed load"); in LowerPredicateLoad()
10170 assert(LD->isUnindexed() && "Loads should be unindexed at this point."); in LowerLOAD()
10194 assert(ST->isUnindexed() && "Expected a unindexed store"); in LowerPredicateStore()
10228 assert(ST->isUnindexed() && "Stores should be unindexed at this point."); in LowerSTORE()
15203 if (LN0->hasOneUse() && LN0->isUnindexed() && in PerformVMOVhrCombine()
16521 if (LD && Op.hasOneUse() && LD->isUnindexed() && in PerformVDUPCombine()
16639 if (!St->isSimple() || St->isTruncatingStore() || !St->isUnindexed()) in PerformSplittingToNarrowingStores()
16732 if (!St->isSimple() || St->isTruncatingStore() || !St->isUnindexed()) in PerformSplittingMVETruncToNarrowingStores()
16773 if (!St->isSimple() || St->isTruncatingStore() || !St->isUnindexed()) in PerformExtractFpToIntStores()
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| H A D | ARMISelDAGToDAG.cpp | 3655 if (Subtarget->isThumb1Only() && ST->isUnindexed()) { in Select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.td | 465 cast<MaskedLoadSDNode>(N)->isUnindexed() &&
474 cast<MaskedLoadSDNode>(N)->isUnindexed();
496 cast<MaskedLoadSDNode>(N)->isUnindexed();
518 cast<MaskedLoadSDNode>(N)->isUnindexed() &&
527 cast<MaskedStoreSDNode>(N)->isUnindexed() &&
535 cast<MaskedStoreSDNode>(N)->isUnindexed();
557 cast<MaskedStoreSDNode>(N)->isUnindexed() &&
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| H A D | AArch64ISelDAGToDAG.cpp | 1579 if (LD->isUnindexed()) in tryIndexedLoad()
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| H A D | AArch64ISelLowering.cpp | 22035 if (MLD->isUnindexed() && MLD->getExtensionType() != ISD::SEXTLOAD && in performUnpackCombine()
22934 Value.getNode()->hasOneUse() && ST->isUnindexed() && in performSTORECombine()
22982 MST->isUnindexed() && Mask->getOpcode() == AArch64ISD::PTRUE && in performMSTORECombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 5964 if (LD->isUnindexed() && LD->hasOneUse() && Op1.hasOneUse() && in Select()
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| H A D | PPCISelLowering.cpp | 15876 if (cast<StoreSDNode>(N)->isUnindexed() && Opcode == ISD::BSWAP && in PerformDAGCombine()
16064 if (LD->isUnindexed() && VT.isVector() && in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 5677 if (Op.getOpcode() == ISD::LOAD && cast<LoadSDNode>(Op)->isUnindexed()) in isVectorElementLoad()
|