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Searched refs:isTypeLegalForClass (Results 1 – 16 of 16) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp242 else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8)) in storeRegToStack()
244 else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) || in storeRegToStack()
245 TRI->isTypeLegalForClass(*RC, MVT::v8f16)) in storeRegToStack()
247 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) || in storeRegToStack()
248 TRI->isTypeLegalForClass(*RC, MVT::v4f32)) in storeRegToStack()
250 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) || in storeRegToStack()
251 TRI->isTypeLegalForClass(*RC, MVT::v2f64)) in storeRegToStack()
320 else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8)) in loadRegFromStack()
322 else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) || in loadRegFromStack()
323 TRI->isTypeLegalForClass(*RC, MVT::v8f16)) in loadRegFromStack()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.cpp145 if (TRI->isTypeLegalForClass(*RC, MVT::i8)) { in storeRegToStackSlot()
147 } else if (TRI->isTypeLegalForClass(*RC, MVT::i16)) { in storeRegToStackSlot()
176 if (TRI->isTypeLegalForClass(*RC, MVT::i8)) { in loadRegFromStackSlot()
178 } else if (TRI->isTypeLegalForClass(*RC, MVT::i16)) { in loadRegFromStackSlot()
H A DAVRRegisterInfo.cpp98 if (TRI->isTypeLegalForClass(*RC, MVT::i16)) { in getLargestLegalSuperClass()
102 if (TRI->isTypeLegalForClass(*RC, MVT::i8)) { in getLargestLegalSuperClass()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.cpp95 if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) && in getMaximalPhysRegClass()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h313 bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const { in isTypeLegalForClass() function
321 bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const { in isTypeLegalForClass() function
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp222 if ((IsDefault || TRI->isTypeLegalForClass(*RC, Ty)) && RC->contains(Reg) && in getMinimalPhysRegClass()
251 if ((IsDefault || TRI->isTypeLegalForClass(*RC, Ty)) && in getCommonMinimalPhysRegClass()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyAsmPrinter.cpp69 if (TRI->isTypeLegalForClass(*TRC, T)) in getRegType()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp160 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg()
H A DSelectionDAGBuilder.cpp9800 !TRI.isTypeLegalForClass(*RC, OpInfo.ConstraintVT)) { in getRegistersForValue()
H A DTargetLowering.cpp5867 if (RI->isTypeLegalForClass(*RC, VT)) in getRegForInlineAsmConstraint()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp2180 assert(TRI->isTypeLegalForClass(*RC, MVT::i32) && "Invalid destination!"); in emitEHSjLjSetJmp()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp23079 if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy)) in getRegForInlineAsmConstraint()
23092 if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy)) in getRegForInlineAsmConstraint()
23096 if (TRI->isTypeLegalForClass(RISCV::VMV0RegClass, VT.SimpleTy)) in getRegForInlineAsmConstraint()
23268 if (TRI->isTypeLegalForClass(RISCV::VMRegClass, VT.SimpleTy)) in getRegForInlineAsmConstraint()
23270 if (TRI->isTypeLegalForClass(RISCV::VRRegClass, VT.SimpleTy)) in getRegForInlineAsmConstraint()
23274 if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy)) { in getRegForInlineAsmConstraint()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp8185 TRI->isTypeLegalForClass(LoongArch::LSX128RegClass, VT)) in getRegForInlineAsmConstraint()
8188 TRI->isTypeLegalForClass(LoongArch::LASX256RegClass, VT)) in getRegForInlineAsmConstraint()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp1008 assert(TRI->isTypeLegalForClass(*RC, MVT::i32) && "Invalid destination!"); in emitEHSjLjSetJmp()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp37023 assert(TRI->isTypeLegalForClass(*RC, MVT::i32) && "Invalid destination!"); in emitEHSjLjSetJmp()
61916 if (TRI->isTypeLegalForClass(*Res.second, VT) || VT == MVT::Other) in getRegForInlineAsmConstraint()
61981 else if (TRI->isTypeLegalForClass(X86::VR128XRegClass, VT)) in getRegForInlineAsmConstraint()
61983 else if (TRI->isTypeLegalForClass(X86::VR256XRegClass, VT)) in getRegForInlineAsmConstraint()
61985 else if (TRI->isTypeLegalForClass(X86::VR512RegClass, VT)) in getRegForInlineAsmConstraint()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp13265 assert(TRI->isTypeLegalForClass(*RC, MVT::i32) && "Invalid destination!"); in emitEHSjLjSetJmp()