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Searched refs:isTop (Results 1 – 7 of 7) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMachineScheduler.cpp35 SchedCandidate &FirstCand = Zone.isTop() ? TryCand : Cand; in biasAddiLoadCandidate()
36 SchedCandidate &SecondCand = Zone.isTop() ? Cand : TryCand; in biasAddiLoadCandidate()
141 if ((Zone->isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum) || in tryCandidate()
142 (!Zone->isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) { in tryCandidate()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DVLIWMachineScheduler.h180 MaxPath = std::max(MaxPath, isTop() ? SU.getHeight() : SU.getDepth()); in init()
185 bool isTop() const { in isTop()
206 unsigned PathLength = isTop() ? SU->getHeight() : SU->getDepth(); in isLatencyBound()
184 bool isTop() const { isTop() function
H A DMachineScheduler.h964 bool isTop() const { in isTop() function
985 return isTop() ? SU->getHeight() : SU->getDepth(); in getUnscheduledLatency()
1234 LLVM_ABI unsigned getWeakLeft(const SUnit *SU, bool isTop);
1235 LLVM_ABI int biasPhysReg(const SUnit *SU, bool isTop);
1314 void reschedulePhysReg(SUnit *SU, bool isTop);
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineScheduler.cpp2615 unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle); in getLatencyStallCycles()
2627 if (isTop()) in getNextResourceCycleByInstance()
2640 if (!isTop()) in getNextResourceCycleByInstance()
2748 ((isTop() && SchedModel->mustBeginGroup(SU->getInstr())) || in checkHazard()
2749 (!isTop() && SchedModel->mustEndGroup(SU->getInstr())))) { in checkHazard()
2751 << (isTop() ? "begin" : "end") << " group\n"); in checkHazard()
2903 if (isTop()) in bumpCycle()
2974 if (!isTop() && SU->isCall) { in bumpNode()
2991 unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle); in bumpNode()
3060 if (isTop()) { in bumpNode()
[all …]
H A DVLIWMachineScheduler.cpp398 if (isTop()) in bumpCycle()
416 if (!isTop() && SU->isCall) { in bumpNode()
425 startNewCycle = ResourceModel->reserveResources(SU, isTop()); in bumpNode()
449 unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle; in releasePending()
489 return !ResourceModel->isResourceAvailable(*Available.begin(), isTop()) || in pickOnlyChoice()
490 getWeakLeft(*Available.begin(), isTop()) != 0; in pickOnlyChoice()
497 ResourceModel->reserveResources(nullptr, isTop()); in pickOnlyChoice()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNSchedStrategy.cpp349 initCandidate(TryCand, SU, Zone.isTop(), RPTracker, SRI, SGPRPressure, in pickNodeFromQueue()
616 if ((Zone->isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum) || in tryCandidate()
617 (!Zone->isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) { in tryCandidate()
704 if (tryGreater(Zone->isTop() ? TryLongLatency : CandLongLatency, in tryCandidate()
705 Zone->isTop() ? CandLongLatency : TryLongLatency, TryCand, in tryCandidate()
746 if (Zone->isTop() == (TryCand.SU->NodeNum < Cand.SU->NodeNum)) { in tryCandidate()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstPropagation.cpp142 bool isTop() const { return Kind == Top; } in isTop() function in __anonfe19b4d40111::LatticeCell
193 assert(Top.isTop()); in CellMap()
448 uint32_t Ps = !isTop() ? properties() in convertToProperty()
485 } else if (isTop()) { in print()
505 if (isBottom() || L.isTop()) in meet()
507 if (isTop()) { in meet()
586 assert(!isTop() && "Should not call this for a top cell"); in properties()
2212 assert(!Input.isTop()); in evaluate()