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Searched refs:isSubRegister (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCInstrDesc.cpp35 if (ImpDef == Reg || (MRI && MRI->isSubRegister(Reg, ImpDef))) in hasImplicitDefOfPhysReg()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfExpression.h63 bool isSubRegister() const { return SubRegSize; } in isSubRegister() function
H A DDwarfExpression.cpp352 assert(!Reg.isSubRegister() && "full register expected"); in addMachineRegExpression()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp624 unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R; in checkRegisters()
637 unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R; in checkRegisters()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRFrameLowering.cpp264 if (STI.getRegisterInfo()->isSubRegister(LiveIn.PhysReg, Reg)) { in spillCalleeSavedRegisters()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h484 bool isSubRegister(MCRegister RegA, MCRegister RegB) const { in isSubRegister() function
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineInstr.cpp1148 Found = TRI->isSubRegister(MOReg, Reg); in findRegisterDefOperandIdx()
2148 if (RegInfo->isSubRegister(IncomingReg, Reg)) in addRegisterKilled()
2212 if (RegInfo->isSubRegister(Reg, MOReg)) in addRegisterDead()
H A DLiveVariables.cpp243 if (TRI->isSubRegister(Reg, DefReg)) in FindLastPartialDef()
H A DAggressiveAntiDepBreaker.cpp582 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters()
H A DMachineCopyPropagation.cpp582 if (!TRI->isSubRegister(PreviousSrc, Src)) in isNopCopy()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp997 if (TRI->isSuperRegister(Reg, DestReg) || TRI->isSubRegister(Reg, DestReg)) in describeLoadedValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp720 assert(!isSubRegister(ScratchRSrcReg, StackPtrReg)); in getReservedRegs()
726 assert(!isSubRegister(ScratchRSrcReg, FrameReg)); in getReservedRegs()
732 assert(!isSubRegister(ScratchRSrcReg, BasePtrReg)); in getReservedRegs()
H A DSIFrameLowering.cpp1797 assert(RegBlock && TRI->isSubRegister(RegBlock, Reg) && in assignSlotsUsingVGPRBlocks()
H A DSIInstrInfo.cpp4758 return TRI.isSubRegister(SuperVec.getReg(), SubReg.getReg()); in isSubRegOf()
H A DSIISelLowering.cpp16764 assert(!TRI->isSubRegister(Info->getScratchRSrcReg(), in finalizeLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp2510 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg)) in findMatchingUpdateInsnForward()
2616 if (DestReg[i] == BaseReg || TRI->isSubRegister(BaseReg, DestReg[i])) in findMatchingUpdateInsnBackward()
H A DAArch64InstrInfo.cpp10155 TRI->isSubRegister(DestReg, DescribedReg)) { in describeORRLoadedValue()