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Searched refs:isSpilledToReg (Results 1 – 7 of 7) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaFrameLowering.cpp82 if (MBBI->getOpcode() == TargetOpcode::COPY && Info.isSpilledToReg()) { in emitPrologue()
167 if (I->getOpcode() == TargetOpcode::COPY && Info.isSpilledToReg()) { in emitEpilogue()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DPrologEpilogInserter.cpp479 if (CS.isSpilledToReg()) in assignCalleeSavedSpillSlots()
582 if (I.isSpilledToReg()) { in updateLiveness()
608 if (CS.isSpilledToReg()) { in insertCSRSaves()
636 if (CI.isSpilledToReg()) { in insertCSRRestores()
H A DMIRPrinter.cpp469 if (!CSInfo.isSpilledToReg() && MFI.isDeadObjectIndex(FrameIdx)) in convertStackObjects()
474 if (!CSInfo.isSpilledToReg()) { in convertStackObjects()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp751 if (CSI.isSpilledToReg()) { in emitPrologue()
1211 if (I.isSpilledToReg()) { in emitPrologue()
1684 if (CSI.isSpilledToReg()) { in emitEpilogue()
2220 if (!GPRegs[i].isSpilledToReg()) { in processFunctionBeforeFrameFinalized()
2229 if (!G8Regs[i].isSpilledToReg()) { in processFunctionBeforeFrameFinalized()
2426 if (Info.isSpilledToReg()) { in spillCalleeSavedRegisters()
2485 if (I.isSpilledToReg()) { in spillCalleeSavedRegisters()
2657 if (CSI[i].isSpilledToReg()) { in restoreCalleeSavedRegisters()
H A DPPCRegisterInfo.cpp483 if (CSI.isSpilledToReg()) in requiresFrameIndexScavenging()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineFrameInfo.h74 bool isSpilledToReg() const { return SpilledToReg; } in isSpilledToReg() function
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp612 assert(!Info.isSpilledToReg() && "Spilling to registers not implemented"); in emitCalleeSavedGPRLocations()
654 assert(!Info.isSpilledToReg() && "Spilling to registers not implemented"); in emitCalleeSavedSVELocations()