Searched refs:isSignExtended (Results 1 – 7 of 7) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 125 bool isSignExtended(Register R, MachineRegisterInfo &MRI) { in isSignExtended() function
169 (isSignExtended(LHS, MRI) || isZeroExtended(LHS, MRI))) in matchAArch64MulConstCombine()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 727 bool isSignExtended(const unsigned Reg, in isSignExtended() function
|
| H A D | PPCMIPeephole.cpp | 1049 TII->isSignExtended(NarrowReg, MRI)) { in simplifyCode()
|
| H A D | PPCInstrInfo.cpp | 2443 if (isSignExtended(SrcReg, MRI)) in optimizeCompareInstr()
|
| H A D | PPCISelLowering.cpp | 12980 static bool isSignExtended(MachineInstr &MI, const PPCInstrInfo *TII) { in isSignExtended() function
12985 return TII->isSignExtended(MI.getOperand(1).getReg(), in isSignExtended()
13050 incr.isVirtual() && isSignExtended(*RegInfo.getVRegDef(incr), TII); in EmitPartwordAtomicBinary()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9521 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { in isSignExtended() function
9662 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
9688 bool isN0SExt = isSignExtended(N0, DAG); in LowerMUL()
9689 bool isN1SExt = isSignExtended(N1, DAG); in LowerMUL()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 5213 static bool isSignExtended(SDValue N, SelectionDAG &DAG) { in isSignExtended() function
5231 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); in isAddSubSExt()
5375 bool IsN0SExt = isSignExtended(N0, DAG); in selectUmullSmull()
5376 bool IsN1SExt = isSignExtended(N1, DAG); in selectUmullSmull()
18906 if (N0->hasOneUse() && (isSignExtended(N0, DAG) || in performMulCombine()
|