Searched refs:isShiftedMask (Results 1 – 13 of 13) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVInstructionSelector.cpp | 422 if (Mask.isShiftedMask()) { in selectSHXADDOp()
464 if (LeftShift.has_value() && Mask.isShiftedMask()) { in selectSHXADDOp()
512 if (Mask.isShiftedMask()) { in selectSHXADD_UWOp()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/ADT/ |
| H A D | APInt.h | 510 bool isShiftedMask() const { in isShiftedMask() function
522 bool isShiftedMask(unsigned &MaskIdx, unsigned &MaskLen) const { in isShiftedMask() function
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 757 if (!AndMask.isShiftedMask(LowZBits, MaskLen)) in SelectShiftedRegisterFromAnd()
3334 static bool isShiftedMask(uint64_t Mask, EVT VT) { in isShiftedMask() function
3378 if (!isShiftedMask(Known.Zero.getZExtValue(), VT)) in tryBitfieldInsertOpFromOrAndImm()
3733 (isShiftedMask(Mask0Imm, VT) || isShiftedMask(Mask1Imm, VT))) { in tryBitfieldInsertOpFromOr()
3738 if (isShiftedMask(Mask0Imm, VT)) { in tryBitfieldInsertOpFromOr()
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| H A D | AArch64ISelLowering.cpp | 17960 if (XorC->getAPIntValue().isShiftedMask(MaskIdx, MaskLen)) { in isDesirableToCommuteXorWithShift()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 620 if (ImmValue.isNegative() && ImmValue.isShiftedMask()) { in selectVSplatMaskL()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 2225 if (MaskC->getValue().isShiftedMask(MaskIdx, MaskLen)) { in instCombineIntrinsic()
2269 if (MaskC->getValue().isShiftedMask(MaskIdx, MaskLen)) { in instCombineIntrinsic()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoZb.td | 218 if (!Imm.isShiftedMask())
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | PatternMatch.h | 512 bool isValue(const APInt &C) const { return C.isShiftedMask(); } in isValue()
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| /freebsd/contrib/llvm-project/clang/lib/Sema/ |
| H A D | SemaChecking.cpp | 3248 if (Result.isShiftedMask() || (~Result).isShiftedMask()) in ValueIsRunOfOnes()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 4279 if (Mask->getAPIntValue().isShiftedMask(MaskIdx, MaskLen) && in performSrlCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 15376 } else if (Mask.isShiftedMask(ShAmt, ActiveBits)) { in reduceLoadWidth()
15451 ShiftMask.isShiftedMask(Offset, ActiveBits) && in reduceLoadWidth()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 13926 if (XorC->getAPIntValue().isShiftedMask(MaskIdx, MaskLen)) { in isDesirableToCommuteXorWithShift()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Testing/Demangle/ |
| H A D | DemangleTestCases.inc | 18822 {"_ZN4llvm8APIntOps13isShiftedMaskEjRKNS_5APIntE", "llvm::APIntOps::isShiftedMask(unsigned int, llv…
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