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Searched refs:isShiftedInt (Results 1 – 25 of 25) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepOperands.td18 defm s6_0ImmPred : ImmOpPred<[{ return isShiftedInt<6, 0>(N->getSExtValue());}]>;
21 defm s32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
30 defm m32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
33 defm b13_2ImmPred : ImmOpPred<[{ return isShiftedInt<13, 2>(N->getSExtValue());}]>;
36 defm b15_2ImmPred : ImmOpPred<[{ return isShiftedInt<15, 2>(N->getSExtValue());}]>;
39 defm a30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
42 defm b30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
45 defm s31_1ImmPred : ImmOpPred<[{ return isShiftedInt<32, 1>(N->getSExtValue());}]>;
48 defm s30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
51 defm s29_3ImmPred : ImmOpPred<[{ return isShiftedInt<32, 3>(N->getSExtValue());}]>;
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H A DHexagonInstrInfo.cpp2945 return isShiftedInt<11,1>(Offset); in isValidOffset()
2949 return isShiftedInt<11,2>(Offset); in isValidOffset()
4112 isShiftedInt<6,3>(MI.getOperand(1).getImm())) in getDuplexCandidateGroup()
H A DHexagonPatterns.td2674 return isShiftedInt<30,2>(v) && !isShiftedInt<29,3>(v);
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZicbo.td20 ImmLeaf<XLenVT, [{return isShiftedInt<7, 5>(Imm);}]> {
27 return isShiftedInt<7, 5>(Imm);
H A DRISCVInstrInfoC.td145 ImmLeaf<XLenVT, [{return isShiftedInt<8, 1>(Imm);}]> {
153 return isShiftedInt<8, 1>(Imm);
195 [{return (Imm != 0) && isShiftedInt<6, 4>(Imm);}]> {
204 return isShiftedInt<6, 4>(Imm) && (Imm != 0);
210 ImmLeaf<XLenVT, [{return isShiftedInt<11, 1>(Imm);}]> {
218 return isShiftedInt<11, 1>(Imm);
H A DRISCVInstrInfoZb.td181 return !isInt<13>(C) && !isShiftedInt<20, 12>(C) && isShiftedInt<12, 2>(C);
190 return !isInt<14>(C) && !isShiftedInt<20, 12>(C) && isShiftedInt<12, 3>(C);
H A DRISCVRegisterInfo.cpp271 if (isShiftedInt<12, 3>(Val)) { in adjustReg()
274 } else if (isShiftedInt<12, 2>(Val)) { in adjustReg()
H A DRISCVInstrInfo.cpp2409 Ok = isShiftedInt<6, 4>(Imm) && (Imm != 0); in verifyInstruction()
2439 Ok = isShiftedInt<7, 5>(Imm); in verifyInstruction()
H A DRISCVInstrInfo.td261 return isShiftedInt<12, 1>(Imm);
312 return isShiftedInt<20, 1>(Imm);
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYAsmBackend.cpp190 return !isShiftedInt<10, 1>(Offset); in fixupNeedsRelaxationAdvanced()
192 return !isShiftedInt<16, 1>(Offset); in fixupNeedsRelaxationAdvanced()
194 return !isShiftedInt<26, 1>(Offset); in fixupNeedsRelaxationAdvanced()
/freebsd/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/JITLink/
H A Dloongarch.h199 if (!isShiftedInt<26, 2>(Value)) in applyFixup()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/
H A DLoongArchAsmParser.cpp234 return IsConstantImm && isShiftedInt<N, S>(Imm) && in isSImm()
364 ? isShiftedInt<16, 2>(Imm) && IsValidKind in isSImm16lsl2()
481 ? isShiftedInt<21, 2>(Imm) && IsValidKind in isSImm21lsl2()
498 ? isShiftedInt<26, 2>(Imm) && IsValidKind in isSImm26Operand()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.h209 return isShiftedInt<N, S>(minConstant(MCI, Index)); in inSRange()
H A DHexagonMCDuplexInfo.cpp546 if (!isShiftedInt<7, 0>(Value)) in subInstWouldBeExtended()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp2327 return !isShiftedInt<11, 1>( in lowerINTRINSIC_W_CHAIN()
2334 return !isShiftedInt<10, 2>( in lowerINTRINSIC_W_CHAIN()
2341 return !isShiftedInt<9, 3>( in lowerINTRINSIC_W_CHAIN()
2480 return (!isShiftedInt<8, 1>( in lowerINTRINSIC_VOID()
2487 return (!isShiftedInt<8, 1>( in lowerINTRINSIC_VOID()
2494 return (!isShiftedInt<8, 2>( in lowerINTRINSIC_VOID()
2501 return (!isShiftedInt<8, 2>( in lowerINTRINSIC_VOID()
2508 return (!isShiftedInt<8, 3>( in lowerINTRINSIC_VOID()
2515 return (!isShiftedInt<8, 3>( in lowerINTRINSIC_VOID()
6080 !(isShiftedInt<14, 2>(AM.BaseOffs) && Subtarget.hasUAL())) in isLegalAddressingMode()
H A DLoongArchInstrInfo.td352 ImmLeaf<GRLenVT, [{return isShiftedInt<14,2>(Imm);}]> {
443 ImmLeaf<GRLenVT, [{return isShiftedInt<16, 16>(Imm);}]>;
448 return !isInt<12>(Imm) && isShiftedInt<16, 16>(Imm - SignExtend64<12>(Imm));
/freebsd/contrib/llvm-project/lld/MachO/Arch/
H A DARM64.cpp296 return ldr.p2Size > 1 && isShiftedInt<19, 2>(ldr.offset); in isLiteralLdrEligible()
/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DMathExtras.h186 constexpr bool isShiftedInt(int64_t x) { in isShiftedInt() function
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp582 isShiftedInt<16, 8>(Value)) in LowerImmediate()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp519 IsValid = isShiftedInt<N - 1, 1>(Imm); in isBareSimmNLsb0()
919 return IsConstantImm && isShiftedInt<7, 5>(Imm) && in isSImm12Lsb00000()
931 return IsConstantImm && (Imm != 0) && isShiftedInt<6, 4>(Imm) && in isSImm10Lsb0000NonZero()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/
H A DCSKYAsmParser.cpp265 return IsConstantImm && isShiftedInt<num, shift>(Imm); in isSImm()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1358 isShiftedInt<Bits, ShiftAmount>(getConstantMemOff()))) in isMemWithSimmOffset()
1362 return IsReloc && isShiftedInt<Bits, ShiftAmount>(Res.getConstant()); in isMemWithSimmOffset()
1409 isShiftedInt<Bits, ShiftLeftAmount>(getConstantImm())) in isScaledSImm()
1417 return Success && isShiftedInt<Bits, ShiftLeftAmount>(Res.getConstant()); in isScaledSImm()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1722 isShiftedInt<7, 3>(NewOffset)) { in matchLDPSTPAddrMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.td128 ImmLeaf<i32, "return isShiftedInt<"#num#", "#shift#">(Imm);"> {
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16973 if (isShiftedInt<16, 16>(Value)) in LowerAsmOperandForConstraint()