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Searched refs:isShiftedInt (Results 1 – 25 of 28) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepOperands.td18 defm s6_0ImmPred : ImmOpPred<[{ return isShiftedInt<6, 0>(N->getSExtValue());}]>;
21 defm s32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
30 defm m32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>;
33 defm b13_2ImmPred : ImmOpPred<[{ return isShiftedInt<13, 2>(N->getSExtValue());}]>;
36 defm b15_2ImmPred : ImmOpPred<[{ return isShiftedInt<15, 2>(N->getSExtValue());}]>;
39 defm a30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
42 defm b30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
45 defm s31_1ImmPred : ImmOpPred<[{ return isShiftedInt<32, 1>(N->getSExtValue());}]>;
48 defm s30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>;
51 defm s29_3ImmPred : ImmOpPred<[{ return isShiftedInt<32, 3>(N->getSExtValue());}]>;
[all …]
H A DHexagonInstrInfo.cpp2949 return isShiftedInt<11,1>(Offset); in isValidOffset()
2953 return isShiftedInt<11,2>(Offset); in isValidOffset()
4116 isShiftedInt<6,3>(MI.getOperand(1).getImm())) in getDuplexCandidateGroup()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.cpp154 OffsetLegal = isShiftedInt<8, 1>(FixedOffset); in eliminateFrameIndex()
158 OffsetLegal = isShiftedInt<8, 2>(FixedOffset); in eliminateFrameIndex()
162 OffsetLegal = isShiftedInt<8, 3>(FixedOffset); in eliminateFrameIndex()
H A DLoongArchInstrInfo.td322 ImmLeaf<GRLenVT, [{return isShiftedInt<8,1>(Imm);}]> {
329 ImmLeaf<GRLenVT, [{return isShiftedInt<8,2>(Imm);}]> {
336 ImmLeaf<GRLenVT, [{return isShiftedInt<8,3>(Imm);}]> {
343 ImmLeaf<GRLenVT, [{return isShiftedInt<9,3>(Imm);}]> {
354 ImmLeaf<GRLenVT, [{return isShiftedInt<10,2>(Imm);}]> {
361 ImmLeaf<GRLenVT, [{return isShiftedInt<11,1>(Imm);}]> {
390 ImmLeaf<GRLenVT, [{return isShiftedInt<14,2>(Imm);}]> {
481 ImmLeaf<GRLenVT, [{return isShiftedInt<16, 16>(Imm);}]>;
486 return !isInt<12>(Imm) && isShiftedInt<16, 16>(Imm - SignExtend64<12>(Imm));
H A DLoongArchISelLowering.cpp3490 return !isShiftedInt<11, 1>( in lowerINTRINSIC_W_CHAIN()
3497 return !isShiftedInt<10, 2>( in lowerINTRINSIC_W_CHAIN()
3504 return !isShiftedInt<9, 3>( in lowerINTRINSIC_W_CHAIN()
3643 return (!isShiftedInt<8, 1>( in lowerINTRINSIC_VOID()
3650 return (!isShiftedInt<8, 1>( in lowerINTRINSIC_VOID()
3657 return (!isShiftedInt<8, 2>( in lowerINTRINSIC_VOID()
3664 return (!isShiftedInt<8, 2>( in lowerINTRINSIC_VOID()
3671 return (!isShiftedInt<8, 3>( in lowerINTRINSIC_VOID()
3678 return (!isShiftedInt<8, 3>( in lowerINTRINSIC_VOID()
8362 !(isShiftedInt<14, 2>(AM.BaseOffs) && Subtarget.hasUAL())) in isLegalAddressingMode()
/freebsd/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/JITLink/
H A Dloongarch.h360 if (!isShiftedInt<16, 2>(Value)) in applyFixup()
375 if (!isShiftedInt<21, 2>(Value)) in applyFixup()
391 if (!isShiftedInt<26, 2>(Value)) in applyFixup()
448 if (!isShiftedInt<36, 2>(Value)) in applyFixup()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYAsmBackend.cpp173 return !isShiftedInt<10, 1>(Offset); in fixupNeedsRelaxationAdvanced()
175 return !isShiftedInt<16, 1>(Offset); in fixupNeedsRelaxationAdvanced()
177 return !isShiftedInt<26, 1>(Offset); in fixupNeedsRelaxationAdvanced()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZicbo.td20 ImmLeaf<XLenVT, [{return isShiftedInt<7, 5>(Imm);}]> {
H A DRISCVInstrInfoC.td142 ImmLeaf<XLenVT, [{return isShiftedInt<8, 1>(Imm);}]> {
150 return isShiftedInt<8, 1>(Imm);
191 [{return (Imm != 0) && isShiftedInt<6, 4>(Imm);}]> {
200 return isShiftedInt<6, 4>(Imm) && (Imm != 0);
206 ImmLeaf<XLenVT, [{return isShiftedInt<11, 1>(Imm);}]> {
214 return isShiftedInt<11, 1>(Imm);
H A DRISCVInstrInfoZb.td180 return !isInt<13>(C) && !isShiftedInt<20, 12>(C) && isShiftedInt<12, 2>(C);
189 return !isInt<14>(C) && !isShiftedInt<20, 12>(C) && isShiftedInt<12, 3>(C);
H A DRISCVRegisterInfo.cpp360 if (isShiftedInt<12, 3>(Val)) { in adjustReg()
363 } else if (isShiftedInt<12, 2>(Val)) { in adjustReg()
H A DRISCVInstrInfo.td348 return isShiftedInt<12, 1>(Imm);
358 ImmLeaf<XLenVT, [{return isShiftedInt<12, 1>(Imm);}]> {
395 ImmLeaf<XLenVT, [{return isShiftedInt<20, 1>(Imm);}]> {
403 return isShiftedInt<20, 1>(Imm);
H A DRISCVInstrInfoXAndes.td26 return isShiftedInt<10, 1>(Imm);
H A DRISCVInstrInfo.cpp2854 Ok = isShiftedInt<6, 4>(Imm) && (Imm != 0); in verifyInstruction()
2894 Ok = isShiftedInt<7, 5>(Imm); in verifyInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.h209 return isShiftedInt<N, S>(minConstant(MCI, Index)); in inSRange()
H A DHexagonMCDuplexInfo.cpp546 if (!isShiftedInt<7, 0>(Value)) in subInstWouldBeExtended()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/
H A DLoongArchAsmParser.cpp277 return IsConstantImm && isShiftedInt<N, S>(Imm) && in isSImm()
399 ? isShiftedInt<16, 2>(Imm) && IsValidKind in isSImm16lsl2()
509 ? isShiftedInt<21, 2>(Imm) && IsValidKind in isSImm21lsl2()
523 ? isShiftedInt<26, 2>(Imm) && IsValidKind in isSImm26Operand()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp543 return isShiftedInt<N - 1, 1>(fixImmediateForRV32(Imm, isRV64Imm())); in isBareSimmNLsb0()
877 return isSImmPred([](int64_t Imm) { return isShiftedInt<7, 5>(Imm); }); in isSImm12Lsb00000()
882 [](int64_t Imm) { return Imm != 0 && isShiftedInt<6, 4>(Imm); }); in isSImm10Lsb0000NonZero()
958 return isSImmPred([](int64_t Imm) { return isShiftedInt<17, 1>(Imm); }); in isSImm18Lsb0()
962 return isSImmPred([](int64_t Imm) { return isShiftedInt<17, 2>(Imm); }); in isSImm19Lsb00()
966 return isSImmPred([](int64_t Imm) { return isShiftedInt<17, 3>(Imm); }); in isSImm20Lsb000()
970 return isSImmPred([](int64_t Imm) { return isShiftedInt<31, 1>(Imm); }); in isSImm32Lsb0()
/freebsd/contrib/llvm-project/lld/MachO/Arch/
H A DARM64.cpp328 return ldr.p2Size > 1 && isShiftedInt<19, 2>(ldr.offset); in isLiteralLdrEligible()
/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DMathExtras.h187 constexpr bool isShiftedInt(int64_t x) { in isShiftedInt() function
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/
H A DCSKYAsmParser.cpp265 return IsConstantImm && isShiftedInt<num, shift>(Imm); in isSImm()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1310 isShiftedInt<Bits, ShiftAmount>(getConstantMemOff()))) in isMemWithSimmOffset()
1314 return IsReloc && isShiftedInt<Bits, ShiftAmount>(Res.getConstant()); in isMemWithSimmOffset()
1361 isShiftedInt<Bits, ShiftLeftAmount>(getConstantImm())) in isScaledSImm()
1369 return Success && isShiftedInt<Bits, ShiftLeftAmount>(Res.getConstant()); in isScaledSImm()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp953 isShiftedInt<8, 8>(Value)) in LowerImmediate()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1863 isShiftedInt<7, 3>(NewOffset)) { in matchLDPSTPAddrMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.td128 ImmLeaf<i32, "return isShiftedInt<"#num#", "#shift#">(Imm);"> {

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