Searched refs:isSMRD (Results 1 – 7 of 7) sorted by relevance
143 if (SIInstrInfo::isSMRD(MI)) in getHardClauseType()
102 return SIInstrInfo::isSMRD(MI); in isSMEMClauseInst()
194 if (SIInstrInfo::isSMRD(*MI) && checkSMRDHazards(MI) > 0) in getHazardType()336 if (SIInstrInfo::isSMRD(*MI)) in PreEmitNoopsCommon()614 return !SIInstrInfo::isSMRD(*MI); in breaksSMEMSoftClause()627 bool IsSMRD = TII.isSMRD(*MEM); in checkSoftClauseHazards()1152 if (!SIInstrInfo::isSALU(*MI) && !SIInstrInfo::isSMRD(*MI)) in fixVMEMtoScalarWriteHazards()1231 return SIInstrInfo::isSMRD(I) && I.readsRegister(SDSTReg, TRI); in fixSMEMtoVectorWriteHazards()
330 if (TII->isSMRD(MI) || TII->isVMEM(MI) || TII->isFLAT(MI) || in mustRetainExeczBranch()
544 static bool isSMRD(const MachineInstr &MI) { in isSMRD() function548 bool isSMRD(uint16_t Opcode) const { in isSMRD() function
114 if (SIInstrInfo::isSMRD(MI)) { in canRemat()276 if (isSMRD(Opc0) && isSMRD(Opc1)) { in areLoadsFromSameBasePtr()481 if (isSMRD(LdSt)) { in getMemOperandsWithOffsetWidth()3758 return !isSMRD(MIb); in areMemAccessesTriviallyDisjoint()3761 if (isSMRD(MIa)) { in areMemAccessesTriviallyDisjoint()3762 if (isSMRD(MIb)) in areMemAccessesTriviallyDisjoint()4122 if (MI.mayStore() && isSMRD(MI)) in hasUnwantedEffectsWhenEXECEmpty()4596 SIInstrInfo::isSMRD(MI)) in shouldReadExec()5114 if (isSMRD(MI)) { in verifyInstruction()6573 if (isSMRD(MI)) { in legalizeOperands()[all …]
2033 } else if (TII->isSMRD(Inst)) { in updateEventWaitcntAfter()2232 if (TII->isSMRD(Inst)) { in insertWaitcntInBlock()