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Searched refs:isSGPRReg (Results 1 – 13 of 13) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILowerI1Copies.h76 return TII->getRegisterInfo().isSGPRReg(*MRI, Reg) && in isLaneMaskReg()
H A DSIOptimizeExecMasking.cpp650 if (!TRI->isSGPRReg(*MRI, SaveExecDest)) in tryRecordVCmpxAndSaveexecSequence()
682 if (Src0->isReg() && TRI->isSGPRReg(*MRI, Src0->getReg()) && in tryRecordVCmpxAndSaveexecSequence()
687 if (Src1->isReg() && TRI->isSGPRReg(*MRI, Src1->getReg()) && in tryRecordVCmpxAndSaveexecSequence()
H A DSIFixSGPRCopies.cpp712 if ((Src0.isReg() && TRI->isSGPRReg(*MRI, Src0.getReg()) && in runOnMachineFunction()
714 (Src1.isReg() && TRI->isSGPRReg(*MRI, Src1.getReg()) && in runOnMachineFunction()
955 if (TRI->isSGPRReg(*MRI, Reg) && !TII->isVALU(*Inst)) in analyzeVGPRToSGPRCopy()
H A DSIFoldOperands.cpp952 if (TRI->isSGPRReg(*MRI, Src.Reg)) { in foldOperand()
1023 if (OpToFold.isReg() && TRI->isSGPRReg(*MRI, OpToFold.getReg())) { in foldOperand()
1244 bool IsSGPR = TRI->isSGPRReg(*MRI, MI->getOperand(0).getReg()); in tryConstantFoldOp()
1587 if (TRI->isSGPRReg(*MRI, DefReg)) { in tryFoldClamp()
1988 TRI->isSGPRReg(*MRI, CopyIn.getReg())) in tryFoldPhiAGPR()
H A DSIRegisterInfo.h207 bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const;
H A DGCNHazardRecognizer.cpp969 if (TRI->isSGPRReg(MRI, UseReg)) { in checkVALUHazards()
1058 if (!LaneSelectOp->isReg() || !TRI->isSGPRReg(MRI, LaneSelectOp->getReg())) in checkRWLaneHazards()
2861 if (TRI.isSGPRReg(MRI, OpReg)) in fixVALUMaskWriteHazard()
H A DSIInstrInfo.cpp3613 RI.isSGPRReg(*MRI, Src0->getReg())) { in foldImmediate()
3626 else if (RI.isSGPRReg(*MRI, Src1->getReg())) in foldImmediate()
3946 !RI.isSGPRReg(MBB.getParent()->getRegInfo(), Src0->getReg()))) { in convertToThreeAddress()
4172 if (!RI.isSGPRReg(MRI, MI.getOperand(0).getReg())) in mayReadEXEC()
5320 if (Src->isReg() && RI.isSGPRReg(MRI, Src->getReg())) { in verifyInstruction()
5811 RI.isSGPRReg(MRI, MO->getReg())) in isOperandLegal()
5863 RI.isSGPRReg(MRI, Src0.getReg())) in legalizeOperandsVOP2()
6134 if (RI.isSGPRReg(MRI, SAddr.getReg())) in moveFlatAddrToVGPR()
8095 if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg())) { in splitScalar64BitXnor()
H A DSIPeepholeSDWA.cpp1221 TRI->isSGPRReg(*MRI, Op.getReg())) { in legalizeScalarOperands()
H A DSIInstrInfo.h1016 return !RI.isSGPRReg(MRI, Dest); in isVGPRCopy()
H A DAMDGPUCallLowering.cpp73 if (TRI->isSGPRReg(MRI, PhysReg)) { in assignValueToReg()
H A DSIInsertWaitcnts.cpp757 } else if (TRI->isSGPRReg(*MRI, Op.getReg())) { in getRegInterval()
H A DSIRegisterInfo.cpp2870 bool SIRegisterInfo::isSGPRReg(const MachineRegisterInfo &MRI, in isSGPRReg() function in SIRegisterInfo
H A DSIISelLowering.cpp15248 !TRI->isSGPRReg(MRI, Src->getOperand(1).getReg())) in AdjustInstrPostInstrSelection()
15969 return !TRI->isSGPRReg(MRI, Reg); in isSDNodeSourceOfDivergence()
15975 return !TRI->isSGPRReg(MRI, Reg); in isSDNodeSourceOfDivergence()