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Searched refs:isSGPRClass (Results 1 – 14 of 14) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h226 static bool isSGPRClass(const TargetRegisterClass *RC) { in isSGPRClass() function
232 return isSGPRClass(getRegClass(RCID)); in isSGPRClassID()
237 return isSGPRClass(getPhysRegBaseClass(Reg)); in isSGPRPhysReg()
336 return !isSGPRClass(RC); in isDivergentRegClass()
H A DSIFixSGPRCopies.cpp226 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) && in isVGPRToSGPRCopy()
233 return DstRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(SrcRC) && in isSGPRToVGPRCopy()
285 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
329 assert(TRI->isSGPRClass(SrcRC) && in foldVGPRCopyIntoRegSequence()
668 if (TRI->isSGPRClass(TII->getOpRegClass(MI, 0))) { in run()
H A DSIInstrInfo.cpp207 RI.isSGPRClass(MRI.getRegClass(Op.getReg()))) { in isSafeToSink()
1046 if (RC == RI.getVGPR64Class() && (SrcRC == RC || RI.isSGPRClass(SrcRC))) { in copyPhysReg()
1069 if (RI.isSGPRClass(RC)) { in copyPhysReg()
1070 if (!RI.isSGPRClass(SrcRC)) { in copyPhysReg()
1086 (ST.hasGFX90AInsts() && RI.isSGPRClass(SrcRC))) in copyPhysReg()
1094 (SrcRC == RC || RI.isSGPRClass(SrcRC)))) { in copyPhysReg()
1394 return RI.isSGPRClass(DstRC) ? AMDGPU::COPY : AMDGPU::V_MOV_B16_t16_e64; in getMovOpcode()
1397 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; in getMovOpcode()
1398 if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) in getMovOpcode()
1400 if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) in getMovOpcode()
[all …]
H A DGCNPreRAOptimizations.cpp256 if ((RC->MC->getSizeInBits() != 64 || !TRI->isSGPRClass(RC)) && in run()
H A DAMDGPURegBankLegalize.cpp124 return RC && TRI.isSGPRClass(RC) && MRI.getType(Reg) == LLT::scalar(1); in isLaneMask()
H A DGCNRegPressure.cpp41 return STI->isSGPRClass(RC) ? SGPR : (STI->isAGPRClass(RC) ? AGPR : VGPR); in getRegKind()
411 if (SRI->isSGPRClass(RC)) in isSaveBeneficial()
H A DAMDGPUTargetMachine.cpp147 return static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(RC); in onlyAllocateSGPRs()
154 return !static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(RC); in onlyAllocateVGPRs()
163 return !static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(RC) && in onlyAllocateWWMRegs()
H A DSIRegisterInfo.cpp692 if (RC->isBaseClass() && isSGPRClass(RC)) { in getReservedRegs()
3082 bool IsSALU = isSGPRClass(TII->getOpRegClass(*MI, FIOperandNum)); in eliminateFrameIndex()
3599 return RC && isSGPRClass(RC); in isSGPRReg()
H A DGCNHazardRecognizer.cpp1310 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegBaseClass(MO.getReg()))) { in fixSMEMtoVectorWriteHazards()
1396 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegBaseClass(MO.getReg()))) in fixVcmpxExecWARHazard()
H A DAMDGPUTargetTransformInfo.cpp944 if (!RC || !TRI->isSGPRClass(RC)) in isInlineAsmSourceOfDivergence()
H A DAMDGPUISelDAGToDAG.cpp1656 return RC && TRI.isSGPRClass(RC); in IsCopyFromSGPR()
3929 if (!RC || SIRI->isSGPRClass(RC)) in isVGPRImm()
H A DSIISelLowering.cpp4903 if (TII->getRegisterInfo().isSGPRClass(IdxRC)) { in emitIndirectSrc()
5006 if (TII->getRegisterInfo().isSGPRClass(IdxRC)) { in emitIndirectDst()
5102 bool isSGPR = TRI->isSGPRClass(MRI.getRegClass(SrcReg)); in lowerWaveReduce()
16504 else if (SIRegisterInfo::isSGPRClass(RC)) in getRegForInlineAsmConstraint()
17539 if (!TRI->isSGPRClass(RC) && !isDivergent) in getRegClassFor()
17541 if (TRI->isSGPRClass(RC) && isDivergent) in getRegClassFor()
17620 if (RC && SIRI->isSGPRClass(RC)) in requiresUniformRegister()
H A DAMDGPURegisterBankInfo.cpp294 if (TRI->isSGPRClass(&RC)) { in getRegBankFromRegClass()
H A DAMDGPUInstructionSelector.cpp180 bool IsSGPR = TRI.isSGPRClass(SrcRC); in selectCOPY()