Searched refs:isSGPR (Results 1 – 7 of 7) sorted by relevance
495 if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) { in getSDWASrcEncoding()640 if (AMDGPU::isSGPR(SrcReg, &MRI)) in getMachineOpValueT16()
72 bool isSGPR(Register Reg) const;
2748 bool AMDGPUInstructionSelector::isSGPR(Register Reg) const { in isSGPR() function in AMDGPUInstructionSelector3325 if (!isSGPR(Addr)) { in selectGlobalLoadLds()3327 if (isSGPR(AddrDef->Reg)) { in selectGlobalLoadLds()3332 if (isSGPR(SAddr)) { in selectGlobalLoadLds()3342 if (isSGPR(Addr)) { in selectGlobalLoadLds()3354 if (isSGPR(Addr)) in selectGlobalLoadLds()4378 if (isSGPR(PtrBaseDef->Reg)) { in selectGlobalSAddr()4430 if (isSGPR(SAddr)) { in selectGlobalSAddr()4452 AddrDef->MI->getOpcode() == AMDGPU::G_CONSTANT || !isSGPR(AddrDef->Reg)) in selectGlobalSAddr()4507 isSGPR(RHSDef->Reg)) { in selectScratchSAddr()[all …]
4855 bool isSGPR = TRI->isSGPRClass(MRI.getRegClass(SrcReg)); in lowerWaveReduce() local4858 if (isSGPR) { in lowerWaveReduce()
1314 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
2233 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) { in isSGPR() function
3688 return isSGPR(PReg, TRI) && PReg != SGPR_NULL; in usesConstantBus()3809 return (Opr.isReg() && !isSGPR(mc2PseudoReg(Opr.getReg()), TRI)) in validateVOPDRegBankConstraints()4069 if (!isSGPR(Reg, TRI)) in validateMovrels()4097 if (!isGFX90A() && isSGPR(Reg, TRI)) { in validateMAIAccWrite()4625 if (Src1.isReg() && isSGPR(mc2PseudoReg(Src1.getReg()), TRI)) { in validateDPP()