| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 287 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), in optimizeSDPattern()
333 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass)) in hasPartialWrite()
395 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() || in getReadDPRs()
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| H A D | ARMBaseInstrInfo.cpp | 4222 ResolvedDefMI->isRegSequence() || ResolvedDefMI->isImplicitDef()) { in getOperandLatency()
4560 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() || in getPredicationCost()
4581 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() || in getInstrLatency()
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| H A D | ARMInstrVFP.td | 1326 let isRegSequence = 1;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 282 assert(MI.isRegSequence()); in foldVGPRCopyIntoRegSequence()
703 else if (MI.isRegSequence()) in run()
787 if (MI->isRegSequence()) in run()
825 if (UseMI->isCopy() || UseMI->isRegSequence()) { in processPHINode()
949 if (Inst->isCopy() || Inst->isRegSequence()) { in analyzeVGPRToSGPRCopy()
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| H A D | SIFoldOperands.cpp | 923 assert(RegSeq.isRegSequence()); in getRegSeqInit()
963 if (!Def || !Def->isRegSequence()) in getRegSeqInit()
1156 if (UseMI->isRegSequence()) { in foldOperand()
1813 if (!RegSeq || !RegSeq->isRegSequence()) in foldCopyToAGPRRegSequence()
2032 if (InstToErase && InstToErase->isRegSequence() && in tryFoldFoldableCopy()
2321 assert(MI.isRegSequence()); in tryFoldRegSequence()
2595 if (!I->isCopy() && !I->isRegSequence()) in tryFoldLoad()
2747 if (MI.isRegSequence() && tryFoldRegSequence(MI)) { in run()
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| H A D | AMDGPURegisterBankInfo.cpp | 3852 if (MI.isRegSequence()) { in getInstrMapping()
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| H A D | SIInstrInfo.cpp | 9766 assert(MI.isRegSequence()); in getRegSequenceSubReg()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ProcessImplicitDefs.cpp | 71 !MI->isRegSequence() && in canTurnIntoImplicitDef()
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| H A D | PeepholeOptimizer.cpp | 379 assert(MI.isRegSequence() && "Invalid instruction"); in RegSequenceRewriter()
503 (!DisableAdvCopyOpt && (MI.isRegSequence() || MI.isInsertSubreg() || in isCoalescableCopy()
1962 assert((Def->isRegSequence() || Def->isRegSequenceLike()) && in getNextSourceFromRegSequence()
2145 if (Def->isRegSequence() || Def->isRegSequenceLike()) in getNextSourceImpl()
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| H A D | RegisterBankInfo.cpp | 220 if (MI.isRegSequence()) { in getInstrMappingImpl()
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| H A D | TargetInstrInfo.cpp | 1964 assert((MI.isRegSequence() || in getRegSequenceInputs()
1967 if (!MI.isRegSequence()) in getRegSequenceInputs()
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| H A D | MachineLICM.cpp | 1360 if (MI.isCopy() || MI.isRegSequence()) { in IsProfitableToHoist()
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| H A D | TwoAddressInstructionPass.cpp | 1861 if (mi->isRegSequence()) in run()
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| H A D | MachinePipeliner.cpp | 1996 if (!SU.getInstr()->isCopy() && !SU.getInstr()->isRegSequence()) in apply()
2031 if (TmpMI->isPHI() || TmpMI->isRegSequence()) { in apply()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | InstrDocsEmitter.cpp | 144 FLAG(isRegSequence) in EmitInstrDocs()
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| H A D | InstrInfoEmitter.cpp | 1193 if (Inst.isRegSequence) in emitRecord()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenInstruction.h | 277 bool isRegSequence : 1; variable
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| H A D | CodeGenInstruction.cpp | 459 isRegSequence = R->getValueAsBit("isRegSequence"); in CodeGenInstruction()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 659 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
1421 bool isRegSequence() const {
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 466 if ((DstInst->isRegSequence() || DstInst->isCopy())) { in adjustSchedDependency()
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| H A D | HexagonGenInsert.cpp | 931 bool Skip = MI.isCopy() || MI.isRegSequence(); in collectInBlock()
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| H A D | HexagonConstPropagation.cpp | 1946 if (MI.isRegSequence()) { in evaluate()
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| H A D | HexagonDepInstrInfo.td | 32569 let isRegSequence = 1;
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | Target.td | 669 bit isRegSequence = false; // Is this instruction a kind of reg sequence?
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