| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | LiveRegUnits.h | 53 if (O->isRegMask()) in accumulateUsedDefed()
169 return MOP.isRegMask() || in phys_regs_and_masks()
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| H A D | MachineOperand.h | 352 bool isRegMask() const { return OpKind == MO_RegisterMask; } in isRegMask() function
474 if ((isReg() && isImplicit()) || isRegMask()) in isValidExcessOperand()
661 assert(isRegMask() && "Wrong MachineOperand accessor"); in getRegMask()
738 assert(isRegMask() && "Wrong MachineOperand mutator"); in setRegMask()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveRegUnits.cpp | 53 if (MOP.isRegMask()) { in stepBackward()
80 if (MOP.isRegMask()) { in accumulate()
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| H A D | LivePhysRegs.cpp | 47 if (MOP.isRegMask()) { in removeDefs()
99 } else if (O->isRegMask()) { in stepForward()
110 if (Reg.second->isRegMask() && in stepForward()
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| H A D | RegUsageInfoPropagate.cpp | 60 if (MO.isRegMask()) in setRegMask()
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| H A D | CriticalAntiDepBreaker.cpp | 263 if (MO.isRegMask()) { in ScanInstruction()
368 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg)) in isNewRegClobberedByRefs()
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| H A D | MachineCopyPropagation.cpp | 367 if (MO.isRegMask()) in findAvailBackwardCopy()
399 if (MO.isRegMask()) in findAvailCopy()
428 if (MO.isRegMask()) in findLastSeenDefInCopy()
952 if (MO.isRegMask()) in ForwardCopyPropagateBlock()
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| H A D | MachineInstrBundle.cpp | 321 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) { in AnalyzePhysRegInBundle()
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| H A D | MachineCSE.cpp | 241 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) in isPhysDefTriviallyDead()
382 if (MO.isRegMask()) in PhysRegDefsReach()
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| H A D | RDFGraph.cpp | 597 if (Op.isRegMask()) in isClobbering()
996 assert(Op.isReg() || Op.isRegMask()); in makeRegRef()
1319 if (!Op.isRegMask()) in buildStmt()
1836 if (!Op.isReg() && !Op.isRegMask()) in hasUntrackedRef()
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| H A D | RDFRegisters.cpp | 74 if (Op.isRegMask()) in PhysicalRegisterInfo()
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| H A D | ImplicitNullChecks.cpp | 239 auto IsRegMask = [](const MachineOperand &MO) { return MO.isRegMask(); }; in canHandle()
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| H A D | ShrinkWrap.cpp | 366 } else if (MO.isRegMask()) { in INITIALIZE_PASS_DEPENDENCY()
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| H A D | VirtRegMap.cpp | 651 if (MO.isRegMask()) in rewrite()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86VZeroUpper.cpp | 159 if (MI.isCall() && MO.isRegMask() && !clobbersAllYmmAndZmmRegs(MO)) in hasYmmOrZmmReg()
175 if (MO.isRegMask()) in callHasRegMask()
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| H A D | X86PreTileConfig.cpp | 110 MI.operands(), [](MachineOperand &MO) { return MO.isRegMask(); }); in isDestructiveCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCCTRLoopsVerify.cpp | 84 } else if (MO.isRegMask()) { in clobbersCTR()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVLIWPacketizer.cpp | 787 if (MO.isRegMask() && MO.clobbersPhysReg(DepReg)) in canPromoteToNewValueStore()
830 if (CheckDef && MO.isRegMask() && MO.clobbersPhysReg(DepReg)) in isImplicitDependency()
1275 if (!OpJ.isRegMask()) in hasRegMaskDependence()
1282 } else if (OpI.isRegMask()) { in hasRegMaskDependence()
1605 } else if (!Op.isRegMask()) { in isLegalToPacketizeTogether()
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| H A D | RDFDeadCode.cpp | 70 if (Op.isRegMask()) { in isLiveInstr()
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| H A D | HexagonTfrCleanup.cpp | 156 if (Mo->isRegMask()) { in updateImmMap()
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| H A D | HexagonBlockRanges.cpp | 349 if (!Op.isRegMask()) in computeInitialLiveRanges()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64A57FPLoadBalancing.cpp | 559 } else if (U.isRegMask()) { in colorChain()
695 } else if (MO.isRegMask()) { in maybeKillChain()
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| H A D | AArch64CollectLOH.cpp | 505 if (MO.isRegMask()) { in handleNormalInst()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DbgEntityHistoryCalculator.cpp | 528 } else if (MO.isRegMask()) { in calculateDbgEntityHistory()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 363 if (MO.isRegMask() && MO.clobbersPhysReg(Lanai::SR)) { in optimizeCompareInstr()
|