| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonDepInstrInfo.td | 628 let isPredicated = 1;
644 let isPredicated = 1;
660 let isPredicated = 1;
680 let isPredicated = 1;
701 let isPredicated = 1;
720 let isPredicated = 1;
741 let isPredicated = 1;
756 let isPredicated = 1;
772 let isPredicated = 1;
786 let isPredicated
[all...] |
| H A D | HexagonVLIWPacketizer.cpp | 367 return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0; in isNewifiable()
569 if (!HII->isPredicated(MI)) in getPredicateSense()
700 if (HII->isPredicated(PacketMI)) { in canPromoteToNewValueStore()
701 if (!HII->isPredicated(MI)) in canPromoteToNewValueStore()
926 if (!HII->isPredicated(*I)) in restrictingDepExistInPacket()
953 assert(QII->isPredicated(MI) && "Must be predicated instruction"); in getPredicatedRegister()
1214 if (HII->isPredicated(I) || HII->isPredicated(J)) in hasDeadDependence()
1254 if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI)) in hasControlDependence()
1475 if (HII->isPredicated(I) && HII->isPredicated(J) && in isLegalToPacketizeTogether()
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| H A D | HexagonInstrFormats.td | 86 bits<1> isPredicated = 0;
87 let TSFlags{10} = isPredicated;
190 let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
301 bits<1> isPredicated = 0;
302 let TSFlags{7} = isPredicated;
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| H A D | HexagonExpandCondsets.cpp | 346 if (HII->isPredicated(*DefI)) in updateKillFlags()
424 if (HII->isPredicated(*DefI)) in updateDeadsInRange()
494 if (!HII->isPredicated(*DefI)) in updateDeadsInRange()
745 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI)) in isPredicable()
781 if (PredValid && HII->isPredicated(*MI)) { in getReachingDefForPred()
939 if (!HII->isPredicated(MI)) in renameInRange()
1012 if (PredValid && HII->isPredicated(MI) && in predicate()
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| H A D | HexagonInstrInfo.h | 224 bool isPredicated(const MachineInstr &MI) const override;
394 bool isPredicated(unsigned Opcode) const;
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| H A D | HexagonPeephole.cpp | 231 if (QII->isPredicated(MI)) { in runOnMachineFunction()
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| H A D | Hexagon.td | 352 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
360 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.cpp | 181 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) { in analyzeBranch()
213 CantAnalyze = !isPredicated(*I); in analyzeBranch()
221 if (!isPredicated(*I) && (isUncondBranchOpcode(I->getOpcode()) || in analyzeBranch()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CriticalAntiDepBreaker.cpp | 177 MI.isCall() || MI.hasExtraSrcRegAllocReq() || TII->isPredicated(MI); in PrescanInstruction()
256 if (!TII->isPredicated(MI)) { in ScanInstruction()
603 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI)) in BreakAntiDependencies()
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| H A D | IfConversion.cpp | 1105 bool isPredicated = TII->isPredicated(MI); in ScanInstructions() local
1117 if (!isPredicated) { in ScanInstructions()
1132 if (BBI.ClobbersPred && !isPredicated) { in ScanInstructions()
1975 bool BB1Predicated = BBI1T != MBB1.end() && TII->isPredicated(*BBI1T); in IfConvertDiamondCommon()
1976 bool BB2NonPredicated = BBI2T != MBB2.end() && !TII->isPredicated(*BBI2T); in IfConvertDiamondCommon()
2067 if (TI != BBI.BB->end() && TII->isPredicated(*TI)) in IfConvertDiamond()
2125 if (I.isDebugInstr() || TII->isPredicated(I)) in PredicateBlock()
2185 if (!TII->isPredicated(I) && !MI->isDebugInstr()) { in CopyAndPredicateBlock()
2248 if (FromTI != FromMBB.end() && !TII->isPredicated(*FromTI)) in MergeBlocks()
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| H A D | TargetSchedule.cpp | 290 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI)) in computeOutputLatency()
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| H A D | AggressiveAntiDepBreaker.cpp | 376 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) || in PrescanInstruction()
453 TII->isPredicated(MI) || MI.isInlineAsm(); in ScanInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.h | 44 bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 872 bool isPredicated = isVectorPredicated(&MI); in producesFalseLanesZero() local
876 return isPredicated; in producesFalseLanesZero()
906 if (MO.isUse() && isPredicated) in producesFalseLanesZero()
952 bool isPredicated = isVectorPredicated(&MI); in ValidateLiveOuts() local
956 if (isPredicated) in ValidateLiveOuts()
962 else if (!isPredicated && retainsOrReduces) { in ValidateLiveOuts()
965 } else if (!isPredicated && MI.getOpcode() != ARM::MQPRCopy) in ValidateLiveOuts()
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| H A D | ARMBlockPlacement.cpp | 269 if (!TII->isPredicated(Terminator) && in moveBasicBlock()
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| H A D | ARMSchedule.td | 155 "ARM_MC::isPredicated",
156 "isPredicated"
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| H A D | ARMBaseInstrInfo.cpp | 371 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) { in analyzeBranch()
425 if (!isPredicated(*I) && in analyzeBranch()
454 if (AllowModify && !isPredicated(MBB.back()) && in analyzeBranch()
561 bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const { in isPredicated() function in ARMBaseInstrInfo
3023 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(*MI)) { in optimizeCompareInstr()
3032 isPredicated(*PotentialAND)) in optimizeCompareInstr()
3151 if (isPredicated(*MI)) in optimizeCompareInstr()
3280 assert(!isPredicated(*MI) && "Can't use flags from predicated instruction"); in optimizeCompareInstr()
3298 if (isPredicated(MI)) in shouldSink()
5048 if (MI.getOpcode() == ARM::VMOVD && !isPredicated(MI)) in getExecutionDomain()
[all …]
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| H A D | ARMSLSHardening.cpp | 119 assert(!TII->isPredicated(MI)); in hardenReturnsAndBRs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.h | 284 bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);
339 bool isPredicated() const;
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| H A D | HexagonMCChecker.cpp | 70 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && in initReg()
442 if (ProducerPredInfo.isPredicated() && in checkNewValues()
443 (!ConsumerPredInfo.isPredicated() || in checkNewValues()
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| H A D | HexagonMCInstrInfo.cpp | 35 bool HexagonMCInstrInfo::PredicateInfo::isPredicated() const { in isPredicated() function in HexagonMCInstrInfo::PredicateInfo
733 bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII, in isPredicated() function in HexagonMCInstrInfo
939 if (!isPredicated(MCII, MCI)) in predicateInfo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.h | 179 bool isPredicated(const MachineInstr &MI) const override;
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| H A D | R600Packetizer.cpp | 79 if (TII->isPredicated(*BI)) in getPreviousVector()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanAnalysis.cpp | 157 unsigned CallIdx = R->getNumOperands() - (R->isPredicated() ? 2 : 1); in inferScalarTypeForRecipe()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | VectorUtils.cpp | 1246 (!isPredicated(B->getParent()) || EnablePredicatedInterleavedMemAccesses)) { in analyzeInterleaving()
1382 if ((isPredicated(BlockA) || isPredicated(BlockB)) && in analyzeInterleaving()
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