| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonDepInstrInfo.td | 628 let isPredicated = 1;
644 let isPredicated = 1;
660 let isPredicated = 1;
680 let isPredicated = 1;
701 let isPredicated = 1;
720 let isPredicated = 1;
741 let isPredicated = 1;
756 let isPredicated = 1;
772 let isPredicated = 1;
786 let isPredicated = 1;
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| H A D | HexagonVLIWPacketizer.cpp | 358 return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0; in isNewifiable()
560 if (!HII->isPredicated(MI)) in getPredicateSense()
691 if (HII->isPredicated(PacketMI)) { in canPromoteToNewValueStore()
692 if (!HII->isPredicated(MI)) in canPromoteToNewValueStore()
917 if (!HII->isPredicated(*I)) in restrictingDepExistInPacket()
944 assert(QII->isPredicated(MI) && "Must be predicated instruction"); in getPredicatedRegister()
1205 if (HII->isPredicated(I) || HII->isPredicated(J)) in hasDeadDependence()
1245 if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI)) in hasControlDependence()
1466 if (HII->isPredicated(I) && HII->isPredicated(J) && in isLegalToPacketizeTogether()
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| H A D | HexagonInstrFormats.td | 86 bits<1> isPredicated = 0;
87 let TSFlags{10} = isPredicated;
190 let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
301 bits<1> isPredicated = 0;
302 let TSFlags{7} = isPredicated;
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| H A D | HexagonExpandCondsets.cpp | 330 if (HII->isPredicated(*DefI)) in updateKillFlags()
407 if (HII->isPredicated(*DefI)) in updateDeadsInRange()
477 if (!HII->isPredicated(*DefI)) in updateDeadsInRange()
728 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI)) in isPredicable()
764 if (PredValid && HII->isPredicated(*MI)) { in getReachingDefForPred()
922 if (!HII->isPredicated(MI)) in renameInRange()
995 if (PredValid && HII->isPredicated(MI) && in predicate()
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| H A D | HexagonInstrInfo.h | 224 bool isPredicated(const MachineInstr &MI) const override;
395 bool isPredicated(unsigned Opcode) const;
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| H A D | HexagonPeephole.cpp | 220 if (QII->isPredicated(MI)) { in runOnMachineFunction()
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| H A D | HexagonInstrInfo.cpp | 654 if (Term != MBB.end() && isPredicated(*Term) && in insertBranch()
1670 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const { in isPredicated() function in HexagonInstrInfo
2256 if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI))) in isDotNewInst()
2494 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode); in isNewValueJump()
2517 assert(isPredicated(MI)); in isPredicatedNew()
2523 assert(isPredicated(Opcode)); in isPredicatedNew()
2541 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const { in isPredicated() function in HexagonInstrInfo
3280 if (Cond.empty() || !isPredicated(Cond[0].getImm())) in predOpcodeHasNot()
3345 if (isPredicated(MI)) { in getBaseAndOffsetPosition()
3878 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form in getDotOldOp()
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| H A D | Hexagon.td | 368 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
376 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.cpp | 181 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) { in analyzeBranch()
213 CantAnalyze = !isPredicated(*I); in analyzeBranch()
221 if (!isPredicated(*I) && (isUncondBranchOpcode(I->getOpcode()) || in analyzeBranch()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMLatencyMutations.cpp | 537 if (DstOpcode == ARM::BUNDLE && TII->isPredicated(*DstMI)) { in makeBundleAssumptions()
543 if (SrcOpcode == ARM::BUNDLE && TII->isPredicated(*SrcMI) && in makeBundleAssumptions()
667 if (TII->isPredicated(*SrcMI) && Dep.isAssignedRegDep() && in modifyBypasses()
685 TII->isPredicated(*DstMI) && !hasImplicitCPSRUse(DstMI)) in modifyBypasses()
909 TII->isPredicated(*DstMI) && !hasImplicitCPSRUse(DstMI)) in modifyBypasses()
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| H A D | ARMLowOverheadLoops.cpp | 866 bool isPredicated = isVectorPredicated(&MI); in producesFalseLanesZero() local
870 return isPredicated; in producesFalseLanesZero()
900 if (MO.isUse() && isPredicated) in producesFalseLanesZero()
946 bool isPredicated = isVectorPredicated(&MI); in ValidateLiveOuts() local
950 if (isPredicated) in ValidateLiveOuts()
956 else if (!isPredicated && retainsOrReduces) { in ValidateLiveOuts()
959 } else if (!isPredicated && MI.getOpcode() != ARM::MQPRCopy) in ValidateLiveOuts()
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| H A D | ARMBlockPlacement.cpp | 269 if (!TII->isPredicated(Terminator) && in moveBasicBlock()
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| H A D | ARMBaseInstrInfo.cpp | 196 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) { in analyzeBranch()
250 if (!isPredicated(*I) && in analyzeBranch()
279 if (AllowModify && !isPredicated(MBB.back()) && in analyzeBranch()
386 bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const { in isPredicated() function in ARMBaseInstrInfo
2866 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(*MI)) { in optimizeCompareInstr()
2875 isPredicated(*PotentialAND)) in optimizeCompareInstr()
2994 if (isPredicated(*MI)) in optimizeCompareInstr()
3123 assert(!isPredicated(*MI) && "Can't use flags from predicated instruction"); in optimizeCompareInstr()
3141 if (isPredicated(MI)) in shouldSink()
4891 if (MI.getOpcode() == ARM::VMOVD && !isPredicated(MI)) in getExecutionDomain()
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| H A D | ARMSchedule.td | 155 "ARM_MC::isPredicated",
156 "isPredicated"
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| H A D | ARMSLSHardening.cpp | 119 assert(!TII->isPredicated(MI)); in hardenReturnsAndBRs()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CriticalAntiDepBreaker.cpp | 177 MI.isCall() || MI.hasExtraSrcRegAllocReq() || TII->isPredicated(MI); in PrescanInstruction()
257 if (!TII->isPredicated(MI)) { in ScanInstruction()
603 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI)) in BreakAntiDependencies()
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| H A D | IfConversion.cpp | 1124 bool isPredicated = TII->isPredicated(MI); in ScanInstructions() local
1136 if (!isPredicated) { in ScanInstructions()
1151 if (BBI.ClobbersPred && !isPredicated) { in ScanInstructions()
1990 bool BB1Predicated = BBI1T != MBB1.end() && TII->isPredicated(*BBI1T); in IfConvertDiamondCommon()
1991 bool BB2NonPredicated = BBI2T != MBB2.end() && !TII->isPredicated(*BBI2T); in IfConvertDiamondCommon()
2082 if (TI != BBI.BB->end() && TII->isPredicated(*TI)) in IfConvertDiamond()
2139 if (I.isDebugInstr() || TII->isPredicated(I)) in PredicateBlock()
2199 if (!TII->isPredicated(I) && !MI->isDebugInstr()) { in CopyAndPredicateBlock()
2262 if (FromTI != FromMBB.end() && !TII->isPredicated(*FromTI)) in MergeBlocks()
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| H A D | TargetSchedule.cpp | 287 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI)) in computeOutputLatency()
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| H A D | AggressiveAntiDepBreaker.cpp | 378 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) || in PrescanInstruction()
455 TII->isPredicated(MI) || MI.isInlineAsm(); in ScanInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.h | 44 bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.h | 284 bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);
339 bool isPredicated() const;
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| H A D | HexagonMCChecker.cpp | 70 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && in initReg()
442 if (ProducerPredInfo.isPredicated() && in checkNewValues()
443 (!ConsumerPredInfo.isPredicated() || in checkNewValues()
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| H A D | HexagonMCInstrInfo.cpp | 35 bool HexagonMCInstrInfo::PredicateInfo::isPredicated() const { in isPredicated() function in HexagonMCInstrInfo::PredicateInfo
733 bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII, in isPredicated() function in HexagonMCInstrInfo
939 if (!isPredicated(MCII, MCI)) in predicateInfo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.h | 181 bool isPredicated(const MachineInstr &MI) const override;
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| H A D | R600Packetizer.cpp | 79 if (TII->isPredicated(*BI)) in getPreviousVector()
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