| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelDAGToDAG.cpp | 156 bool isPre = (AM == ISD::PRE_DEC); in selectIndexedLoad() local
161 if ((!isPre && Offs != 1) || (isPre && Offs != -1)) { in selectIndexedLoad()
165 Opcode = (isPre) ? AVR::LDRdPtrPd : AVR::LDRdPtrPi; in selectIndexedLoad()
169 if ((!isPre && Offs != 2) || (isPre && Offs != -2)) { in selectIndexedLoad()
173 Opcode = (isPre) ? AVR::LDWRdPtrPd : AVR::LDWRdPtrPi; in selectIndexedLoad()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | GenericMachineInstrs.h | 116 bool isPre() const { return getOperand(4).getImm() == 1; } in isPre() function
117 bool isPost() const { return !isPre(); } in isPost()
176 bool isPre() const { return getOperand(4).getImm() == 1; } in isPre() function
177 bool isPost() const { return !isPre(); } in isPost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1594 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryARMIndexedLoad() local
1597 if (LoadedVT == MVT::i32 && isPre && in tryARMIndexedLoad()
1601 } else if (LoadedVT == MVT::i32 && !isPre && in tryARMIndexedLoad()
1607 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG; in tryARMIndexedLoad()
1614 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) in tryARMIndexedLoad()
1615 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); in tryARMIndexedLoad()
1620 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST; in tryARMIndexedLoad()
1623 if (isPre && in tryARMIndexedLoad()
1627 } else if (!isPre && in tryARMIndexedLoad()
1633 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG; in tryARMIndexedLoad()
[all …]
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| H A D | ARMInstrFormats.td | 787 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
794 let Inst{24} = isPre; // P bit
796 let Inst{21} = isPre; // W bit
800 class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops,
803 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
818 class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops,
821 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
837 class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
840 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
876 class AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops,
[all …]
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| /freebsd/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGExprScalar.cpp | 660 bool isInc, bool isPre);
3000 bool isPre, ASTContext &Ctx) { in matchesPostDecrInWhile() argument
3001 if (isInc || isPre) in matchesPostDecrInWhile()
3038 bool isInc, bool isPre) { in EmitScalarPrePostIncDec() argument
3055 if (isPre) { in EmitScalarPrePostIncDec()
3083 return isPre ? Builder.CreateBinOp(op, old, amt) : old; in EmitScalarPrePostIncDec()
3099 return isPre ? Builder.CreateBinOp(op, old, amt) : old; in EmitScalarPrePostIncDec()
3134 matchesPostDecrInWhile(E, isInc, isPre, CGF.getContext()); in EmitScalarPrePostIncDec()
3371 return isPre ? value : input; in EmitScalarPrePostIncDec()
3385 return isPre ? value : input; in EmitScalarPrePostIncDec()
[all …]
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| H A D | CGExprComplex.cpp | 200 bool isInc, bool isPre) { in VisitPrePostIncDec() argument
202 return CGF.EmitComplexPrePostIncDec(E, LV, isInc, isPre); in VisitPrePostIncDec()
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| H A D | CodeGenFunction.h | 3361 bool isInc, bool isPre);
3363 bool isInc, bool isPre);
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| H A D | CGExpr.cpp | 1263 bool isInc, bool isPre) { in EmitComplexPrePostIncDec() argument
1294 return isPre ? IncVal : InVal; in EmitComplexPrePostIncDec()
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| /freebsd/contrib/llvm-project/clang/lib/CIR/CodeGen/ |
| H A D | CIRGenExprScalar.cpp | 401 bool isInc, bool isPre) { in emitScalarPrePostIncDec() argument
530 return isPre ? value : input; in emitScalarPrePostIncDec()
2151 bool isPre) { in emitScalarPrePostIncDec() argument
2153 .emitScalarPrePostIncDec(e, lv, isInc, isPre); in emitScalarPrePostIncDec()
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| H A D | CIRGenFunction.h | 914 bool isInc, bool isPre);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 5554 bool IsPre = ExtLd.isPre(); in selectIndexedExtLoad()
5664 if (Ld.isPre()) { in selectIndexedLoad()
5708 if (I.isPre()) { in selectIndexedStore()
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