Home
last modified time | relevance | path

Searched refs:isPhysical (Results 1 – 25 of 136) sorted by relevance

123456

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRegUnits.cpp48 if (MOP.isDef() && MOP.getReg().isPhysical()) in stepBackward()
64 if (MOP.getReg().isPhysical()) in stepBackward()
73 if (!MOP.getReg().isPhysical()) in accumulate()
H A DAllocationOrder.h115 assert(!Reg.isPhysical() || in isHint()
118 return Reg.isPhysical() && is_contained(Hints, Reg.id()); in isHint()
H A DPeepholeOptimizer.cpp468 if (!Reg.isPhysical()) { in ValueTracker()
511 if (DstReg.isPhysical() || SrcReg.isPhysical()) in INITIALIZE_PASS_DEPENDENCY()
673 SrcReg.isPhysical() || SrcReg2.isPhysical()) in optimizeCmpInstr()
729 if (Reg.isPhysical()) in findNextSource()
741 if (CurSrcPair.Reg.isPhysical()) in findNextSource()
789 if (CurSrcPair.Reg.isPhysical()) in findNextSource()
1236 if (MODef.getReg().isPhysical()) in optimizeCoalescableCopy()
1287 assert(!Def.Reg.isPhysical() && "We do not rewrite physical registers"); in rewriteSource()
1345 if (Def.Reg.isPhysical()) in optimizeUncoalescableCopy()
1503 return Reg.isPhysical() && !MRI->isAllocatable(Reg); in isNAPhysCopy()
[all …]
H A DExpandPostRAPseudos.cpp74 assert(DstReg.isPhysical() && in LowerSubregToReg()
76 assert(InsReg.isPhysical() && in LowerSubregToReg()
H A DLivePhysRegs.cpp88 if (!Reg.isPhysical()) in stepForward()
296 assert(Reg.isPhysical()); in recomputeLivenessFlags()
325 assert(Reg.isPhysical()); in recomputeLivenessFlags()
H A DCalcSpillWeights.cpp215 if (Reg.isPhysical() != Rhs.Reg.isPhysical()) in weightCalcHelper()
216 return Reg.isPhysical(); in weightCalcHelper()
H A DMachineInstrBundle.cpp198 if (!MO->isDead() && Reg.isPhysical()) { in finalizeBundle()
339 assert(Reg.isPhysical() && "analyzePhysReg not given a physical register!"); in AnalyzePhysRegInBundle()
350 if (!MOReg || !MOReg.isPhysical()) in AnalyzePhysRegInBundle()
H A DCodeGenCommonISel.cpp107 (!OPI->getReg().isPhysical() && OPI2->getReg().isPhysical())) in MIIsInTerminatorSequence()
H A DRegAllocFast.cpp858 if (Reg.isPhysical()) in traceCopyChain()
902 if (Hint0.isPhysical() && MRI->isAllocatable(Hint0) && RC.contains(Hint0) && in allocVirtReg()
920 if (Hint1.isPhysical() && MRI->isAllocatable(Hint1) && RC.contains(Hint1) && in allocVirtReg()
1156 assert(Hint.isPhysical() && in useVirtReg()
1310 if (Reg.isPhysical()) { in findAndSortDefOperandIndexes()
1427 } else if (Reg.isPhysical()) { in allocateInstruction()
1510 if (Reg.isPhysical() && MO.getSubReg() != 0) { in allocateInstruction()
1527 assert(Reg.isPhysical()); in allocateInstruction()
1556 if (!Reg.isPhysical()) in allocateInstruction()
1624 assert(Reg.isPhysical() && "should have register assigned"); in allocateInstruction()
H A DRegisterCoalescer.cpp465 if (Src.isPhysical()) { in setRegisters()
466 if (Dst.isPhysical()) in setRegisters()
475 if (Dst.isPhysical()) { in setRegisters()
534 assert(!(Dst.isPhysical() && DstSub) && "Cannot have a physical SubIdx"); in setRegisters()
541 if (DstReg.isPhysical()) in flip()
566 if (DstReg.isPhysical()) { in isCoalescable()
567 if (!Dst.isPhysical()) in isCoalescable()
943 if (NewReg.isPhysical()) in removeCopyByCommutingDef()
1274 assert(!Reg.isPhysical() && "This code cannot handle physreg aliasing"); in definesFullReg()
1295 if (SrcReg.isPhysical()) in reMaterializeTrivialDef()
[all …]
H A DMachineCombiner.cpp172 if (MI->getOperand(0).getSubReg() || Src.isPhysical() || Dst.isPhysical()) in isTransientMI()
181 if (Src.isPhysical() && Dst.isPhysical()) in isTransientMI()
H A DTwoAddressInstructionPass.cpp377 IsSrcPhys = SrcReg.isPhysical(); in isCopyToReg()
378 IsDstPhys = DstReg.isPhysical(); in isCopyToReg()
447 if (Reg.isPhysical() && (allowFalsePositives || MRI->hasOneUse(Reg))) in isKilled()
451 if (Reg.isPhysical()) in isKilled()
510 IsDstPhys = DstReg.isPhysical(); in findOnlyInterestingUse()
520 IsDstPhys = DstReg.isPhysical(); in findOnlyInterestingUse()
538 if (Reg.isPhysical()) in getMappedReg()
1156 } else if (MOReg.isPhysical()) { in rescheduleKillAboveMI()
1203 if (MOReg.isPhysical() && regOverlapsSet(LiveDefs, MOReg)) in rescheduleKillAboveMI()
2041 if (LV && isKill && !SrcReg.isPhysical()) in eliminateRegSequence()
H A DMachineVerifier.cpp147 if (Reg.isPhysical()) in addRegWithSubRegs()
982 if (Reg.isPhysical()) in verifyAllRegOpsScalar()
1123 if (MO->isReg() && MO->getReg().isPhysical()) in verifyPreISelGenericInstruction()
2251 if (SrcReg.isPhysical() && DstTy.isValid()) { in visitMachineInstrBefore()
2258 if (DstReg.isPhysical() && SrcTy.isValid()) { in visitMachineInstrBefore()
2272 if (SrcReg.isPhysical() && DstReg.isVirtual() && DstSize.isScalable() && in visitMachineInstrBefore()
2275 if (SrcReg.isVirtual() && DstReg.isPhysical() && SrcSize.isScalable() && in visitMachineInstrBefore()
2367 if (DstReg.isPhysical()) in visitMachineInstrBefore()
2428 else if (MO->getReg().isPhysical()) { in visitMachineOperand()
2432 else if (MOTied.getReg().isPhysical() && in visitMachineOperand()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFormMemoryClauses.cpp143 if (MO.getReg().isPhysical() && MO.isRenamable()) in getMopState()
173 if (Reg.isPhysical()) in canBundle()
347 if (Reg.isPhysical()) in runOnMachineFunction()
403 if (Reg.isPhysical()) in runOnMachineFunction()
411 if (Reg.isPhysical()) in runOnMachineFunction()
H A DSIPreAllocateWWMRegs.cpp94 if (Reg.isPhysical()) in processDef()
126 if (VirtReg.isPhysical()) in rewriteRegs()
H A DSIPeepholeSDWA.cpp592 if (!Src1->isReg() || Src1->getReg().isPhysical() || in matchSDWAOperand()
593 Dst->getReg().isPhysical()) in matchSDWAOperand()
630 if (!Src1->isReg() || Src1->getReg().isPhysical() || in matchSDWAOperand()
631 Dst->getReg().isPhysical()) in matchSDWAOperand()
692 if (!Src0->isReg() || Src0->getReg().isPhysical() || in matchSDWAOperand()
693 Dst->getReg().isPhysical()) in matchSDWAOperand()
721 if (!ValSrc->isReg() || ValSrc->getReg().isPhysical() || in matchSDWAOperand()
722 Dst->getReg().isPhysical()) in matchSDWAOperand()
H A DSIShrinkInstructions.cpp586 if (Reg.isPhysical() && MO.getReg().isPhysical()) { in instAccessReg()
613 if (Reg.isPhysical()) { in getSubRegForIndex()
783 if (SDstReg.isPhysical() || !MRI->use_nodbg_empty(SDstReg)) in tryReplaceDeadSDST()
823 if (Src.isImm() && MI.getOperand(0).getReg().isPhysical()) { in runOnMachineFunction()
887 if (Src.isImm() && Dst.getReg().isPhysical()) { in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp130 if (Src.isPhysical() || Dst.isPhysical()) in foldSimpleCrossClassCopies()
198 if (UseOp0.isPhysical() || UseOp1.isPhysical()) in foldCopyDup()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp121 (SrcReg.isPhysical() && isARMLowRegister(SrcReg))) && in storeRegToStackSlot()
125 (SrcReg.isPhysical() && isARMLowRegister(SrcReg))) { in storeRegToStackSlot()
150 (DestReg.isPhysical() && isARMLowRegister(DestReg))) && in loadRegFromStackSlot()
154 (DestReg.isPhysical() && isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
H A DMLxExpansionPass.cpp90 if (Reg.isPhysical()) in getAccDefMI()
118 if (Reg.isPhysical() || !MRI->hasOneNonDBGUse(Reg)) in getDefReg()
128 if (Reg.isPhysical() || !MRI->hasOneNonDBGUse(Reg)) in getDefReg()
142 if (Reg.isPhysical()) in hasLoopHazard()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRegUnits.h57 if (!Reg.isPhysical()) in accumulateUsedDefed()
169 (MOP.isReg() && !MOP.isDebug() && MOP.getReg().isPhysical()); in phys_regs_and_masks()
H A DTargetRegisterInfo.h98 if (!Reg.isPhysical()) in contains()
107 if (!Reg1.isPhysical() || !Reg2.isPhysical()) in contains()
452 if (RegA.isPhysical() && RegB.isPhysical()) in regsOverlap()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBlockRanges.cpp271 if (R.Reg.isPhysical()) { in expandToSubRegs()
323 if (R.Reg.isPhysical() && Reserved[R.Reg]) in computeInitialLiveRanges()
340 if (S.Reg.isPhysical() && Reserved[S.Reg]) in computeInitialLiveRanges()
376 assert(!S.Reg.isPhysical() || TRI.subregs(S.Reg).empty()); in computeInitialLiveRanges()
384 assert(!S.Reg.isPhysical() || TRI.subregs(S.Reg).empty()); in computeInitialLiveRanges()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterBankInfo.cpp168 !NonCopyInstr->getOperand(0).getReg().isPhysical()) in addDefUses()
190 !Ret->getOperand(0).getReg().isPhysical() && in skipCopiesOutgoing()
204 !Ret->getOperand(1).getReg().isPhysical()) in skipCopiesIncoming()
344 assert((CopyInst->getOperand(Op).getReg().isPhysical()) && in setTypesAccordingToPhysicalRegister()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp73 if (RN->getReg().isPhysical()) in countOperands()
224 assert(VRBase.isPhysical()); in CreateVirtualRegisters()
532 if (R && R->getReg().isPhysical()) { in EmitSubregNode()
679 if (!R || !R->getReg().isPhysical()) { in EmitRegSequence()
1188 if (Reg.isPhysical()) in EmitMachineNode()
1365 MIB.addReg(Reg, RegState::Define | getImplRegState(Reg.isPhysical())); in EmitSpecialNode()
1373 getImplRegState(Reg.isPhysical())); in EmitSpecialNode()

123456