Home
last modified time | relevance | path

Searched refs:isMask (Results 1 – 24 of 24) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRDFRegisters.cpp143 assert(RR.isMask()); in getUnits()
264 assert(A.isMask()); in print()
280 if (RR.isMask()) in hasAliasOf()
293 if (RR.isMask()) { in hasCoverOf()
308 if (RR.isMask()) { in insert()
H A DRDFGraph.cpp1411 else if (RR.isMask()) in recordDefsForDF()
H A DCodeGenPrepare.cpp7322 if (ActiveBits <= 1 || !DemandBits.isMask(ActiveBits) || in optimizeLoadExt()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenExtract.cpp190 if (M.intersects(C) || !M.isMask(W)) in INITIALIZE_PASS_DEPENDENCY()
196 if (!M.getLoBits(U).isMask(W)) in INITIALIZE_PASS_DEPENDENCY()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DDemandedBits.cpp151 if (AOut.isMask()) { in determineLiveOperandBits()
159 if (AOut.isMask()) { in determineLiveOperandBits()
H A DInstructionSimplify.cpp2425 if (C2->isMask() && // C2 == 0+1+ in simplifyOrInst()
2432 if (C1->isMask() && match(B, m_c_Add(m_Specific(A), m_Value(N)))) { in simplifyOrInst()
H A DScalarEvolution.cpp7894 if (CI->getValue().isMask(Z0TySize)) in createSCEV()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86DomainReassignment.cpp43 static bool isMask(const TargetRegisterClass *RC, in isMask() function
52 if (isMask(RC, TRI)) in getDomain()
H A DX86TargetTransformInfo.cpp6041 Imm.isMask()) in getIntImmCostInst()
H A DX86ISelLowering.cpp48783 NumElts <= CmpBits && CmpVal.isMask(NumElts); in combineSetCCMOVMSK()
50049 if (MaskVal.isMask()) { in combineShiftRightLogical()
51170 if (!X86::isConstantSplat(Op1, SplatVal, false) || !SplatVal.isMask()) in combineAndMaskToShift()
51368 !C1->getAPIntValue().isMask(SubVecVT.getVectorNumElements())) in combineScalarAndWithMaskSetcc()
52697 C2.isMask(VT.getScalarSizeInBits())) in detectUSatPattern()
52702 C1.isNonNegative() && C2.isMask(VT.getScalarSizeInBits())) in detectUSatPattern()
52707 C1.isNonNegative() && C2.isMask(VT.getScalarSizeInBits()) && C2.uge(C1)) in detectUSatPattern()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRDFRegisters.h100 constexpr bool isMask() const { return isMaskId(Reg); } in isMask() function
/freebsd/contrib/llvm-project/llvm/include/llvm/ADT/
H A DAPInt.h488 bool isMask(unsigned numBits) const { in isMask() function
501 bool isMask() const { in isMask() function
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp413 if (!V1.value().isMask(HalfSize) || V2.value() != (1ULL | 1ULL << HalfSize) || in matchCombineMulCMLT()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp649 if (ImmValue.isMask()) { in selectVSplatMaskR()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineAddSub.cpp951 if (C2->isMask()) { in foldAddWithConstant()
2488 if (Op0C->isMask()) { in visitSub()
H A DInstCombineAndOrXor.cpp2492 C->isMask(Width - ShiftC->getZExtValue())) in visitAnd()
2548 C->isMask(X->getType()->getScalarSizeInBits())) { in visitAnd()
2558 C->isMask(X->getType()->getScalarSizeInBits())) { in visitAnd()
H A DInstCombineSelect.cpp700 if (!C1->isMask() || in foldSelectICmpAndZeroShl()
3054 if (!LowBitMaskCst->isMask()) in foldRoundUpIntegerWithPow2Alignment()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DPatternMatch.h669 bool isValue(const APInt &C) const { return C.isMask(); } in isValue()
679 bool isValue(const APInt &C) const { return !C || C.isMask(); } in isValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstCombineIntrinsic.cpp1813 if (NewNumElts >= VWidth && DemandedElts.isMask()) { in simplifyAMDGCNMemoryIntrinsicDemanded()
H A DSIInstrInfo.cpp10282 const auto isMask = [&Mask, SrcSize](const MachineOperand *MO) -> bool { in optimizeCompareInstr() local
10292 if (isMask(SrcOp)) in optimizeCompareInstr()
10294 else if (isMask(&Def->getOperand(2))) in optimizeCompareInstr()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp3985 if (!(AndMask.isMask(AndMaskWidth) && XorMask.countr_one() >= AndMaskWidth)) in foldSubCtlzNot()
6804 if (!AndC->getAPIntValue().isMask()) in isAndLoadExtLoad()
7022 if (!Mask->getAPIntValue().isMask()) in BackwardsPropagateMask()
7411 if (Splat->getAPIntValue().isMask(ElementSize)) { in visitAND()
7617 if (N1C->getAPIntValue().isMask(ScalarWidth) && in visitAND()
7787 if (!C->getAPIntValue().isMask( in visitAND()
13602 ShiftOpc == ISD::SHL ? (~*AndCMask).isMask() : AndCMask->isMask(); in visitSETCC()
15374 if (Mask.isMask()) { in reduceLoadWidth()
15443 if (ShiftMask.isMask()) { in reduceLoadWidth()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp974 if (!MaskVal.isMask()) in matchCombineLoadWithAndMask()
5153 if (!Mask.isMask()) in matchNarrowBinopFeedingAnd()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp16191 if (!V1.isMask(HalfSize) || V2 != (1ULL | 1ULL << HalfSize) || in combineVectorMulToSraBitcast()
19428 if (HiC.isMask(VT.getScalarSizeInBits())) in combineTruncToVnclip()
19436 if (LoC.isNonNegative() && HiC.isMask(VT.getScalarSizeInBits())) in combineTruncToVnclip()
19445 if (LoC.isNonNegative() && HiC.isMask(VT.getScalarSizeInBits()) && in combineTruncToVnclip()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp18772 if (!V1.isMask(HalfSize) || V2 != (1ULL | 1ULL << HalfSize) || in performMulVectorCmpZeroCombine()
24670 if (!SubsAP.isMask()) in performSubsToAndsCombine()