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Searched refs:isMask (Results 1 – 21 of 21) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRDFRegisters.cpp143 assert(RR.isMask()); in getUnits()
264 assert(A.isMask()); in less()
280 if (RR.isMask()) in print()
293 if (RR.isMask()) { in print()
308 if (RR.isMask()) { in hasAliasOf()
H A DCodeGenPrepare.cpp6930 if (ActiveBits <= 1 || !DemandBits.isMask(ActiveBits) || in optimizeLoadExt()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenExtract.cpp201 if (M.intersects(C) || !M.isMask(W)) in INITIALIZE_PASS_DEPENDENCY()
207 if (!M.getLoBits(U).isMask(W)) in INITIALIZE_PASS_DEPENDENCY()
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DDemandedBits.cpp153 if (AOut.isMask()) { in determineLiveOperandBits()
161 if (AOut.isMask()) { in determineLiveOperandBits()
H A DInstructionSimplify.cpp2471 if (C2->isMask() && // C2 == 0+1+ in simplifyOrInst()
2478 if (C1->isMask() && match(B, m_c_Add(m_Specific(A), m_Value(N)))) { in simplifyOrInst()
H A DScalarEvolution.cpp7877 if (CI->getValue().isMask(Z0TySize)) in createSCEV()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86DomainReassignment.cpp51 static bool isMask(const TargetRegisterClass *RC, in isMask() function
60 if (isMask(RC, TRI)) in getDomain()
H A DX86ISelLowering.cpp47019 NumElts <= CmpBits && CmpVal.isMask(NumElts); in combineSetCCMOVMSK()
48294 if (MaskVal.isMask()) { in combineShiftRightLogical()
49427 if (!X86::isConstantSplat(Op1, SplatVal, false) || !SplatVal.isMask()) in combineAndMaskToShift()
49612 !C1->getAPIntValue().isMask(SubVecVT.getVectorNumElements())) in combineScalarAndWithMaskSetcc()
50976 if (C2.isMask(VT.getScalarSizeInBits())) in detectUSatPattern()
50981 if (C1.isNonNegative() && C2.isMask(VT.getScalarSizeInBits())) in detectUSatPattern()
50986 if (C1.isNonNegative() && C2.isMask(VT.getScalarSizeInBits()) && in detectUSatPattern()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRDFRegisters.h100 constexpr bool isMask() const { return isMaskId(Reg); } in isMask() function
/freebsd/contrib/llvm-project/llvm/include/llvm/ADT/
H A DAPInt.h468 bool isMask(unsigned numBits) const { in isMask() function
481 bool isMask() const { in isMask() function
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp413 if (!V1.value().isMask(HalfSize) || V2.value() != (1ULL | 1ULL << HalfSize) || in matchCombineMulCMLT()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstCombineIntrinsic.cpp1386 if (NewNumElts >= VWidth && DemandedElts.isMask()) { in simplifyAMDGCNMemoryIntrinsicDemanded()
H A DSIInstrInfo.cpp9811 const auto isMask = [&Mask, SrcSize](const MachineOperand *MO) -> bool { in optimizeCompareInstr() local
9821 if (isMask(SrcOp)) in optimizeCompareInstr()
9823 else if (isMask(&Def->getOperand(2))) in optimizeCompareInstr()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineAddSub.cpp951 if (C2->isMask()) { in foldAddWithConstant()
2327 if (Op0C->isMask()) { in visitSub()
H A DInstCombineAndOrXor.cpp2415 C->isMask(Width - ShiftC->getZExtValue())) in visitAnd()
2471 C->isMask(X->getType()->getScalarSizeInBits())) { in visitAnd()
2481 C->isMask(X->getType()->getScalarSizeInBits())) { in visitAnd()
H A DInstCombineSelect.cpp654 if (!C1->isMask() || in foldSelectICmpAndZeroShl()
2982 if (!LowBitMaskCst->isMask()) in foldRoundUpIntegerWithPow2Alignment()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DPatternMatch.h669 bool isValue(const APInt &C) { return C.isMask(); } in isValue()
679 bool isValue(const APInt &C) { return !C || C.isMask(); } in isValue()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp6419 if (!AndC->getAPIntValue().isMask()) in isAndLoadExtLoad()
6636 if (!Mask->getAPIntValue().isMask()) in BackwardsPropagateMask()
6989 if (Splat->getAPIntValue().isMask(ElementSize)) { in visitAND()
7194 if (N1C->getAPIntValue().isMask(ScalarWidth) && in visitAND()
7331 if (!C->getAPIntValue().isMask( in visitAND()
12739 ShiftOpc == ISD::SHL ? (~*AndCMask).isMask() : AndCMask->isMask(); in visitSETCC()
14486 if (Mask.isMask()) { in reduceLoadWidth()
14555 if (ShiftMask.isMask()) { in reduceLoadWidth()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp909 if (!MaskVal.isMask()) in matchCombineLoadWithAndMask()
5022 if (!Mask.isMask()) in matchNarrowBinopFeedingAnd()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp14040 if (!V1.isMask(HalfSize) || V2 != (1ULL | 1ULL << HalfSize) || in combineVectorMulToSraBitcast()
16576 if (HiC.isMask(VT.getScalarSizeInBits())) in combineTruncToVnclip()
16584 if (LoC.isNonNegative() && HiC.isMask(VT.getScalarSizeInBits())) in combineTruncToVnclip()
16593 if (LoC.isNonNegative() && HiC.isMask(VT.getScalarSizeInBits()) && in combineTruncToVnclip()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp18188 if (!V1.isMask(HalfSize) || V2 != (1ULL | 1ULL << HalfSize) || in performMulVectorCmpZeroCombine()
23514 if (!SubsAP.isMask()) in performSubsToAndsCombine()