| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRExpandPseudoInsts.cpp | 157 bool DstIsKill = MI.getOperand(1).isKill(); in expandArith()
158 bool SrcIsKill = MI.getOperand(2).isKill(); in expandArith()
190 bool DstIsKill = MI.getOperand(1).isKill(); in expandLogic()
191 bool SrcIsKill = MI.getOperand(2).isKill(); in expandLogic()
249 bool SrcIsKill = MI.getOperand(1).isKill(); in expandLogicImm()
309 bool SrcIsKill = MI.getOperand(1).isKill(); in expand()
363 bool SrcIsKill = MI.getOperand(1).isKill(); in expand()
428 bool DstIsKill = MI.getOperand(1).isKill(); in expand()
461 bool DstIsKill = MI.getOperand(1).isKill(); in expand()
499 bool DstIsKill = MI.getOperand(0).isKill(); in expand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXFMAMutate.cpp | 192 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
196 } else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill() in processBlock()
225 bool AddRegKill = AddendMI->getOperand(1).isKill(); in processBlock()
226 bool KilledProdRegKill = MI.getOperand(KilledProdOp).isKill(); in processBlock()
227 bool OtherProdRegKill = MI.getOperand(OtherProdOp).isKill(); in processBlock()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineInstrBundle.cpp | 165 if (MO.isKill()) in finalizeBundle()
174 if (MO.isKill()) in finalizeBundle()
220 bool isKill = KilledUseSet.count(Reg); in finalizeBundle() local
222 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) | in finalizeBundle()
361 if (MO.isKill()) in AnalyzePhysRegInBundle()
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| H A D | TwoAddressInstructionPass.cpp | 422 return MO.isKill() || isPlainlyKilled(MO.getParent(), MO.getReg()); in isPlainlyKilled()
1022 bool isKill = isPlainlyKilled(MO); in rescheduleMIBelowKill() local
1023 if (MOReg != Reg && ((isKill && regOverlapsSet(Uses, MOReg)) || in rescheduleMIBelowKill()
1027 if (MOReg == Reg && !isKill) in rescheduleMIBelowKill()
1150 bool isKill = isPlainlyKilled(MO); in rescheduleKillAboveMI() local
1151 if (MOReg == Reg && !isKill) in rescheduleKillAboveMI()
1154 if (isKill && MOReg != Reg) in rescheduleKillAboveMI()
1439 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) { in tryInstructionTransform()
1446 if (MO.isKill()) { in tryInstructionTransform()
1814 if (MI->getOperand(SrcIdx).isKill()) in processStatepoint()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VERegisterInfo.cpp | 297 bool isKill = MI.getOperand(3).isKill(); in processSTVM() local
309 build(VE::SVMmr, TmpReg).addReg(SrcReg, getKillRegState(isKill)).addImm(3); in processSTVM()
377 bool isKill = MI.getOperand(3).isKill(); in processSTVM512() local
391 if (isKill) in processSTVM512()
403 if (isKill) { in processSTVM512()
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| H A D | VEInstrInfo.cpp | 461 Register SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
481 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
488 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
495 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
502 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
509 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
516 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
919 bool KillSrc = IsSrcReg ? MI.getOperand(2).isKill() : false; in expandPostRAPseudo()
966 bool KillSrc = MI.getOperand(1).isKill(); in expandPostRAPseudo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstrInfo.h | 138 bool isKill, int FrameIndex, in storeRegToStackSlot() argument
142 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0); in storeRegToStackSlot()
155 Register SrcReg, bool isKill, int FrameIndex,
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| H A D | MipsSEFrameLowering.cpp | 193 .addReg(Src, getKillRegState(I->getOperand(0).isKill())); in expandStoreCCond()
235 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill()); in expandStoreACC()
267 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill()); in expandCopyACC()
326 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, in expandBuildPairF64()
328 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, in expandBuildPairF64()
390 TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, &RegInfo, 0); in expandExtractElementF64()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreRegisterInfo.cpp | 77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
114 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
148 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPImmInst()
193 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPConstInst()
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| H A D | XCoreInstrInfo.h | 71 bool isKill, int FrameIndex,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcInstrInfo.cpp | 529 Register SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
545 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
548 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
551 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
554 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
557 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
562 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.cpp | 38 bool isKill, int FrameIdx, const TargetRegisterClass *RC, in storeRegToStackSlot() argument
53 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
57 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
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| H A D | MSP430InstrInfo.h | 44 bool isKill, int FrameIndex,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPostRABundler.cpp | 187 if (Next != E && Next->isKill()) { in runOnMachineFunction()
195 while (Next != E && Next->isKill()) { in runOnMachineFunction()
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| H A D | SIOptimizeExecMaskingPreRA.cpp | 86 return (!AndLRQ.isKill() && AndLRQ.valueIn() != LR.Query(SelIdx).valueOut()); in isDefBetween()
233 if ((CmpLI && CmpLI->Query(AndIdx.getRegSlot()).isKill()) || in optimizeVcndVcmpPair()
247 bool IsKill = SelLI->Query(CmpIdx.getRegSlot()).isKill(); in optimizeVcndVcmpPair()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineOperand.h | 399 bool isKill() const { in isKill() function
756 /// for liveness related flags (isKill, isUndef and isDead). Note that this
807 bool isKill = false, bool isDead = false,
838 bool isKill = false, bool isDead = false,
845 assert(!(isKill && isDef) && "Kill flag on def");
849 Op.IsDeadOrKill = isKill | isDead;
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| H A D | MachineInstr.h | 1396 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1534 bool isKill = false) const;
1540 bool isKill = false) {
1541 int Idx = findRegisterUseOperandIdx(Reg, TRI, isKill);
1547 bool isKill = false) const {
1549 isKill);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrBuilder.h | 158 unsigned Reg, bool isKill, int Offset) { in addRegOffset() argument
159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | Thumb1InstrInfo.h | 45 bool isKill, int FrameIndex,
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| H A D | Thumb1InstrInfo.cpp | 116 Register SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
135 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 237 if (Op.isReg() && Op.getReg() == RegNotKilled && Op.isKill()) in removeKillInfo()
758 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill()); in emitCombineIR()
805 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill()); in emitCombineRI()
854 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill()); in emitCombineRR()
855 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill()); in emitCombineRR()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaInstrInfo.cpp | 121 bool isKill, int FrameIdx, const TargetRegisterClass *RC, in storeRegToStackSlot() argument
127 .addReg(SrcReg, getKillRegState(isKill)); in storeRegToStackSlot()
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| H A D | XtensaInstrInfo.h | 56 bool isKill, int FrameIndex,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFInstrInfo.h | 40 bool isKill, int FrameIndex,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SIMDInstrOpt.cpp | 435 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement()
437 unsigned Src1IsKill = getKillRegState(MI.getOperand(2).isKill()); in optimizeVectElement()
443 unsigned Src2IsKill = getKillRegState(MI.getOperand(3).isKill()); in optimizeVectElement()
643 StRegKill[i] = getKillRegState(DefiningMI->getOperand(2*i+1).isKill()); in processSeqRegInst()
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