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Searched refs:isKill (Results 1 – 25 of 150) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp155 bool DstIsKill = MI.getOperand(1).isKill(); in expandArith()
156 bool SrcIsKill = MI.getOperand(2).isKill(); in expandArith()
188 bool DstIsKill = MI.getOperand(1).isKill(); in expandLogic()
189 bool SrcIsKill = MI.getOperand(2).isKill(); in expandLogic()
247 bool SrcIsKill = MI.getOperand(1).isKill(); in expandLogicImm()
307 bool SrcIsKill = MI.getOperand(1).isKill(); in expand()
361 bool SrcIsKill = MI.getOperand(1).isKill(); in expand()
426 bool DstIsKill = MI.getOperand(1).isKill(); in expand()
459 bool DstIsKill = MI.getOperand(1).isKill(); in expand()
497 bool DstIsKill = MI.getOperand(0).isKill(); in expand()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp184 if (LIS->getInterval(Reg2).Query(FMAIdx).isKill() in processBlock()
188 } else if (LIS->getInterval(Reg3).Query(FMAIdx).isKill() in processBlock()
217 bool AddRegKill = AddendMI->getOperand(1).isKill(); in processBlock()
218 bool KilledProdRegKill = MI.getOperand(KilledProdOp).isKill(); in processBlock()
219 bool OtherProdRegKill = MI.getOperand(OtherProdOp).isKill(); in processBlock()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineInstrBundle.cpp156 if (MO.isKill()) { in finalizeBundle()
165 if (MO.isKill()) { in finalizeBundle()
209 bool isKill = KilledUseSet.contains(Reg); in finalizeBundle() local
211 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) | in finalizeBundle()
341 if (MO.isKill()) in AnalyzePhysRegInBundle()
H A DTwoAddressInstructionPass.cpp422 return MO.isKill() || isPlainlyKilled(MO.getParent(), MO.getReg()); in isPlainlyKilled()
1024 bool isKill = isPlainlyKilled(MO); in rescheduleMIBelowKill() local
1025 if (MOReg != Reg && ((isKill && regOverlapsSet(Uses, MOReg)) || in rescheduleMIBelowKill()
1029 if (MOReg == Reg && !isKill) in rescheduleMIBelowKill()
1152 bool isKill = isPlainlyKilled(MO); in rescheduleKillAboveMI() local
1153 if (MOReg == Reg && !isKill) in rescheduleKillAboveMI()
1156 if (isKill && MOReg != Reg) in rescheduleKillAboveMI()
1441 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) { in tryInstructionTransform()
1448 if (MO.isKill()) { in tryInstructionTransform()
1816 if (MI->getOperand(SrcIdx).isKill()) in processStatepoint()
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H A DTargetInstrInfo.cpp205 bool Reg1IsKill = MI.getOperand(Idx1).isKill(); in commuteInstructionImpl()
206 bool Reg2IsKill = MI.getOperand(Idx2).isKill(); in commuteInstructionImpl()
797 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI, in foldMemoryOperand()
870 if (MO.isKill() && TRI->regsOverlap(DstReg, MO.getReg())) in transferImplicitOperands()
901 SrcMO.getReg(), SrcMO.isKill(), in lowerCopy()
1355 bool KillA = OpA.isKill(); in reassociateOps()
1356 bool KillX = OpX.isKill(); in reassociateOps()
1357 bool KillY = OpY.isKill(); in reassociateOps()
1535 getKillRegState(Instr->getOperand(2).isKill())) in genAlternativeCodeSequence()
1537 getKillRegState(Instr->getOperand(3).isKill())); in genAlternativeCodeSequence()
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H A DGCEmptyBasicBlocks.cpp64 return !MI.isPosition() && !MI.isImplicitDef() && !MI.isKill() && in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp293 bool isKill = MI.getOperand(3).isKill(); in processSTVM() local
305 build(VE::SVMmr, TmpReg).addReg(SrcReg, getKillRegState(isKill)).addImm(3); in processSTVM()
373 bool isKill = MI.getOperand(3).isKill(); in processSTVM512() local
387 if (isKill) in processSTVM512()
399 if (isKill) { in processSTVM512()
H A DVEInstrInfo.cpp460 Register SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
481 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
488 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
495 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
502 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
509 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
516 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
917 bool KillSrc = IsSrcReg ? MI.getOperand(2).isKill() : false; in expandPostRAPseudo()
964 bool KillSrc = MI.getOperand(1).isKill(); in expandPostRAPseudo()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrInfo.h146 bool isKill, int FrameIndex, const TargetRegisterClass *RC,
149 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0, Flags);
162 Register SrcReg, bool isKill, int FrameIndex,
H A DMipsSEFrameLowering.cpp191 .addReg(Src, getKillRegState(I->getOperand(0).isKill())); in expandStoreCCond()
233 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill()); in expandStoreACC()
265 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill()); in expandCopyACC()
324 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, in expandBuildPairF64()
326 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, in expandBuildPairF64()
388 TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, &RegInfo, 0); in expandExtractElementF64()
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp72 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
109 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
143 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPImmInst()
188 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPConstInst()
H A DXCoreInstrInfo.h72 bool isKill, int FrameIndex, const TargetRegisterClass *RC,
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp528 Register SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
545 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
548 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
551 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
554 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
557 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
562 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp33 bool isKill, int FrameIdx, const TargetRegisterClass *RC, in storeRegToStackSlot() argument
49 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
53 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineOperand.h398 bool isKill() const { in isKill() function
812 bool isKill = false, bool isDead = false,
843 bool isKill = false, bool isDead = false,
850 assert(!(isKill && isDef) && "Kill flag on def");
854 Op.IsDeadOrKill = isKill | isDead;
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPostRABundler.cpp205 if (Next != E && Next->isKill()) { in run()
213 while (Next != E && Next->isKill()) { in run()
H A DSIOptimizeExecMaskingPreRA.cpp94 return (!AndLRQ.isKill() && AndLRQ.valueIn() != LR.Query(SelIdx).valueOut()); in isDefBetween()
241 if ((CmpLI && CmpLI->Query(AndIdx.getRegSlot()).isKill()) || in optimizeVcndVcmpPair()
255 bool IsKill = SelLI->Query(CmpIdx.getRegSlot()).isKill(); in optimizeVcndVcmpPair()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h151 addRegOffset(const MachineInstrBuilder &MIB, Register Reg, bool isKill, in addRegOffset() argument
153 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonCopyToCombine.cpp230 if (Op.isReg() && Op.getReg() == RegNotKilled && Op.isKill()) in removeKillInfo()
751 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill()); in emitCombineIR()
798 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill()); in emitCombineRI()
847 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill()); in emitCombineRR()
848 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill()); in emitCombineRR()
H A DHexagonNewValueJump.cpp647 if (!Op.isReg() || !Op.isUse() || !Op.isKill()) in runOnMachineFunction()
694 cmpInstr->getOperand(0).isKill()) in runOnMachineFunction()
697 cmpInstr->getOperand(1).isKill()) in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp117 Register SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
137 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
H A DThumb1InstrInfo.h46 bool isKill, int FrameIndex, const TargetRegisterClass *RC,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandPseudoInsts.cpp303 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill())) in expandMV_FPR16INX()
320 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill())) in expandMV_FPR32INX()
342 .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill())) in expandRV32ZdinxStore()
351 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill())) in expandRV32ZdinxStore()
357 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill())) in expandRV32ZdinxStore()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.h41 bool isKill, int FrameIndex, const TargetRegisterClass *RC,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SIMDInstrOpt.cpp433 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement()
435 unsigned Src1IsKill = getKillRegState(MI.getOperand(2).isKill()); in optimizeVectElement()
441 unsigned Src2IsKill = getKillRegState(MI.getOperand(3).isKill()); in optimizeVectElement()
641 StRegKill[i] = getKillRegState(DefiningMI->getOperand(2*i+1).isKill()); in processSeqRegInst()

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