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Searched refs:isImm (Results 1 – 25 of 262) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/MCTargetDesc/
H A DXtensaInstPrinter.cpp62 else if (MC.isImm()) in printOperand()
96 if (MI->getOperand(OpNum).isImm()) { in printBranchTarget()
111 if (MC.isImm()) { in printJumpTarget()
127 if (MC.isImm()) { in printCallOperand()
142 if (MC.isImm()) { in printL32RTarget()
159 if (MI->getOperand(OpNum).isImm()) { in printImm8_AsmOperand()
171 if (MI->getOperand(OpNum).isImm()) { in printImm8_sh8_AsmOperand()
183 if (MI->getOperand(OpNum).isImm()) { in printImm12_AsmOperand()
194 if (MI->getOperand(OpNum).isImm()) { in printImm12m_AsmOperand()
205 if (MI->getOperand(OpNum).isImm()) { in printUimm4_AsmOperand()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
H A DVEInstPrinter.cpp56 if (MO.isImm()) { in printOperand()
78 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
84 if (MI->getOperand(OpNum + 1).isImm() && in printMemASXOperand()
86 MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
87 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
95 if (MI->getOperand(OpNum + 1).isImm() && in printMemASXOperand()
101 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
122 if (MI->getOperand(OpNum + 1).isImm() && in printMemASOperandASX()
128 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASOperandASX()
129 if (MI->getOperand(OpNum + 1).isImm() && in printMemASOperandASX()
[all …]
H A DVEMCCodeEmitter.cpp96 if (MO.isImm()) in getMachineOpValue()
121 if (MO.isReg() || MO.isImm()) in getBranchTargetOpValue()
133 if (MO.isImm()) in getCCOpValue()
143 if (MO.isImm()) in getRDOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp229 assert(MO.isImm() && "did not expect relocated expression"); in getLdStUImm12OpValue()
240 if (MO.isImm()) in getLdStUImm12OpValue()
261 if (MO.isImm()) in getAdrLabelOpValue()
292 if (MO.isImm()) in getAddSubImmOpValue()
323 if (MO.isImm()) in getCondBranchTargetOpValue()
346 if (MO.isImm()) in getLoadLiteralOpValue()
368 if (MO.isImm()) in getMoveWideImmOpValue()
396 if (MO.isImm()) in getTestBranchTargetOpValue()
416 if (MO.isImm()) in getBranchTargetOpValue()
438 if (MO.isImm()) in getVecShifterOpValue()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp61 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
231 if (MO.isImm()) return MO.getImm() >> 2;
253 if (MO.isImm()) return MO.getImm() >> 1;
275 if (MO.isImm())
298 if (MO.isImm())
321 if (MO.isImm()) return MO.getImm() >> 1;
342 if (MO.isImm()) return MO.getImm() >> 1;
363 if (MO.isImm()) return MO.getImm() >> 1;
385 if (MO.isImm()) return MO.getImm() >> 2;
407 if (MO.isImm()) retur
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.cpp49 if (MO.isReg() || MO.isImm()) in getDirectBrEncoding()
158 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDispRIEncoding()
171 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDispRIXEncoding()
184 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDispRIX16Encoding()
206 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDispRIHashEncoding()
220 if (MO.isImm()) in getDispRI34PCRelEncoding()
248 if (MO.isImm()) in getDispRI34PCRelEncoding()
262 if (MO.isImm()) in getDispRI34PCRelEncoding()
276 if (MO.isImm()) { in getDispRI34PCRelEncoding()
296 assert(MO.isImm() in getDispRI34Encoding()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp115 if (MCOp.isImm()) in getMachineOpValue()
146 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
154 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
194 assert((Op2.isImm() || Op2.isExpr()) && in getRiMemoryOpValue()
200 if (Op2.isImm()) { in getRiMemoryOpValue()
230 assert(AluMCOp.isImm() && "Third operator is not immediate."); in getRrMemoryOpValue()
265 assert((Op2.isImm() || Op2.isExpr()) && in getSplsOpValue()
271 if (Op2.isImm()) { in getSplsOpValue()
292 if (MCOp.isReg() || MCOp.isImm()) in getBranchTargetOpValue()
H A DLanaiInstPrinter.cpp155 else if (Op.isImm()) in printOperand()
166 if (Op.isImm()) { in printMemImmOperand()
180 if (Op.isImm()) { in printHi16ImmOperand()
192 if (Op.isImm()) { in printHi16AndImmOperand()
204 if (Op.isImm()) { in printLo16AndImmOperand()
229 assert((OffsetOp.isImm() || OffsetOp.isExpr()) && "Immediate expected"); in printMemoryImmediateOffset()
230 if (OffsetOp.isImm()) { in printMemoryImmediateOffset()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp41 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && in getMCRDeprecationInfo()
42 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && in getMCRDeprecationInfo()
45 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { in getMCRDeprecationInfo()
46 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { in getMCRDeprecationInfo()
47 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) { in getMCRDeprecationInfo()
54 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) { in getMCRDeprecationInfo()
61 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && in getMCRDeprecationInfo()
62 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) { in getMCRDeprecationInfo()
68 ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) || in getMCRDeprecationInfo()
69 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) { in getMCRDeprecationInfo()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/AsmParser/
H A DXtensaAsmParser.cpp148 bool isImm() const override { return Kind == Immediate; } in isImm() function
151 bool isImm(int64_t MinValue, int64_t MaxValue) const { in isImm() function
155 bool isImm8() const { return isImm(-128, 127); } in isImm8()
158 return isImm(-32768, 32512) && in isImm8_sh8()
162 bool isImm12() const { return isImm(-2048, 2047); } in isImm12()
168 return isImm(0, 60) && in isOffset4m32()
172 bool isOffset8m8() const { return isImm(0, 255); } in isOffset8m8()
175 return isImm(0, 510) && in isOffset8m16()
180 return isImm(0, 1020) && in isOffset8m32()
184 bool isUimm4() const { return isImm(0, 15); } in isUimm4()
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/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFInstPrinter.cpp62 } else if (Op.isImm()) { in printOperand()
80 if (OffsetOp.isImm()) { in printMemOperand()
94 if (Op.isImm()) in printImm64Operand()
105 if (Op.isImm()) { in printBrTargetOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRMCCodeEmitter.cpp104 assert(MO.isImm()); in encodeRelCondBrTarget()
161 if (OffsetOp.isImm()) { in encodeMemri()
178 assert(MI.getOperand(OpNo).isImm()); in encodeComplement()
206 assert(MO.isImm()); in encodeImm()
221 assert(MO.isImm()); in encodeCallTarget()
261 if (MO.isImm()) in getMachineOpValue()
H A DAVRInstPrinter.cpp133 } else if (Op.isImm()) { in printOperand()
157 if (Op.isImm()) { in printPCRelImm()
184 if (OffsetOp.isImm()) { in printMemri()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiMemAluCombiner.cpp185 (Op.isImm() && Op.getImm() == 0)); in isZeroOperand()
246 assert((AluOffset.isReg() || AluOffset.isImm()) && in insertMergedInstruction()
251 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); in insertMergedInstruction()
265 else if (AluOffset.isImm()) in insertMergedInstruction()
300 if (Op2.isImm()) { in isSuitableAluInstr()
309 if (Offset.isImm() && in isSuitableAluInstr()
374 assert(AluOperand.isImm() && "Unexpected memory operator type"); in combineMemAluInBasicBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCCodeEmitter.cpp110 if (MO.isImm()) { in getMachineOpValue()
130 if (MO2.isImm()) { in getMemOpValue()
158 if (MO.isImm()) in getPCRelImmOpValue()
171 assert(MO.isImm() && "Expr operand expected"); in getCGImmOpValue()
190 assert(MO.isImm() && "Immediate operand expected"); in getCCOpValue()
H A DMSP430InstPrinter.cpp44 if (Op.isImm()) { in printPCRelImmOperand()
62 } else if (Op.isImm()) { in printOperand()
91 assert(Disp.isImm() && "Expected immediate in displacement field"); in printSrcMemOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/MCTargetDesc/
H A DARCInstPrinter.cpp148 if (Op.isImm()) { in printOperand()
162 assert(offset.isImm() && "Offset should be immediate."); in printMemOperandRI()
171 assert(Op.isImm() && "Predicate operand is immediate."); in printPredicateOperand()
178 assert(Op.isImm() && "Predicate operand is immediate."); in printBRCCPredicateOperand()
190 if (MO.isImm()) { in printU6ShiftedBy()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/MCTargetDesc/
H A DM68kInstPrinter.cpp65 if (MO.isImm()) { in printOperand()
77 if (MO.isImm()) in printImmediate()
142 if (Op.isImm()) { in printDisp()
160 assert(MO.isImm() && "absolute memory addressing needs an immediate"); in printAbsMem()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp160 assert(isImm() && "Invalid type access!"); in getImm()
192 bool isImm() const override { return Kind == IMMEDIATE; } in isImm() function
209 if (!isImm()) in isBrImm()
223 bool isCallTarget() { return isImm() || isToken(); } in isCallTarget()
226 if (!isImm()) in isHiImm16()
249 if (!isImm()) in isHiImm16And()
262 if (!isImm()) in isLoImm16()
286 if (!isImm()) in isLoImm16Signed()
310 if (!isImm()) in isLoImm16And()
323 if (!isImm()) in isImmShift()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcMCCodeEmitter.cpp128 if (MO.isImm()) in getMachineOpValue()
153 if (MO.isImm()) in getSImm13OpValue()
210 if (MO.isReg() || MO.isImm()) in getBranchTargetOpValue()
223 if (MO.isReg() || MO.isImm()) in getBranchPredTargetOpValue()
236 if (MO.isReg() || MO.isImm()) in getBranchOnRegTargetOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMacroFusion.cpp85 if (!Op.isImm()) in matchingImmOps()
128 if (!SI.isImm()) in checkOpConstraints()
138 if (!D.isImm()) in checkOpConstraints()
207 if (!SI.isImm() || !RA.isReg()) in checkOpConstraints()
218 if (!SI.isImm() || !RA.isReg()) in checkOpConstraints()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp42 if (FoldOp->isImm()) { in FoldCandidate()
56 bool isImm() const { in isImm() function
208 assert(Old.isReg() && Fold.isImm()); in canUseImmWithOpSel()
362 if (Fold.isImm() && canUseImmWithOpSel(Fold)) { in updateOperand()
376 if ((Fold.isImm() || Fold.isFI() || Fold.isGlobal()) && Fold.needsShrink()) { in updateOperand()
420 if (Fold.isImm()) { in updateOperand()
473 if (!OpToFold->isImm()) in tryAddToFoldList()
492 if (Op2.isImm()) { in tryAddToFoldList()
507 if (!IsLegal && OpToFold->isImm()) { in tryAddToFoldList()
541 if (OpToFold->isImm()) { in tryAddToFoldList()
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H A DGCNDPPCombine.cpp187 if (Op1.isImm()) in getOldOpndValue()
224 assert(RowMaskOpnd && RowMaskOpnd->isImm()); in createDPPInst()
226 assert(BankMaskOpnd && BankMaskOpnd->isImm()); in createDPPInst()
434 assert(OldOpnd->isImm()); in isIdentityValue()
489 if (!CombBCZ && OldOpndValue && OldOpndValue->isImm()) { in createDPPInst()
518 assert(Imm->isImm()); in hasNoImmOrEqual()
544 assert(DppCtrl && DppCtrl->isImm()); in combineDPPMov()
554 assert(RowMaskOpnd && RowMaskOpnd->isImm()); in combineDPPMov()
556 assert(BankMaskOpnd && BankMaskOpnd->isImm()); in combineDPPMov()
561 assert(BCZOpnd && BCZOpnd->isImm()); in combineDPPMov()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp652 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
668 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
684 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
698 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
716 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
810 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
828 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
842 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
860 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
878 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp344 bool isImm() const { return Kind == CV_Immediate; } in isImm() function in __anoncd4cffa40111::CountValue
357 assert(isImm() && "Wrong CountValue accessor"); in getImm()
363 if (isImm()) { OS << Contents.ImmVal; } in print()
682 if (Op2.isImm() || Op1.getReg() == IVReg) in getLoopTripCount()
754 if (!Start->isReg() && !Start->isImm()) in computeCount()
756 if (!End->isReg() && !End->isImm()) in computeCount()
782 if (Start->isImm() && End->isImm()) { in computeCount()
854 bool RegToImm = Start->isReg() && End->isImm(); // for (reg..imm) in computeCount()
858 if (Start->isImm()) in computeCount()
860 if (End->isImm()) in computeCount()
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1234567891011