| /freebsd/contrib/llvm-project/llvm/utils/TableGen/GlobalISel/ |
| H A D | GIMatchDag.cpp | |
| H A D | GIMatchDagOperands.cpp | |
| H A D | GIMatchDagEdge.cpp | |
| H A D | GIMatchDagOperands.h | |
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveIntervalCalc.cpp | 54 if (!MO.isDef() && !MO.readsReg()) in calculate()
71 if (MO.isDef()) in calculate()
79 if (MO.isDef() && !LI.hasSubRanges()) in calculate()
154 if (!MO.readsReg() || (IsSubRange && MO.isDef())) in extendToUses()
160 if (MO.isDef()) in extendToUses()
172 assert(!MO.isDef() && "Cannot handle PHI def of partial register."); in extendToUses()
180 if (MO.isDef()) in extendToUses()
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| H A D | MachineInstrBundle.cpp | 273 if (MO.isDef()) in AnalyzeVirtRegInBundle()
278 if (MO.isDef()) in AnalyzeVirtRegInBundle()
303 if (MO.isDef()) { in AnalyzeVirtRegLanesInBundle()
344 } else if (MO.isDef()) { in AnalyzePhysRegInBundle()
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| H A D | MachineOperand.cpp | 99 if (isDef()) in substPhysReg()
134 if (isDef()) in isRenamable()
285 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp, in ChangeToRegister() argument
299 if (!isDef && MI && MI->isDebugInstr()) in ChangeToRegister()
303 assert(!(isDead && !isDef) && "Dead flag on non-def"); in ChangeToRegister()
304 assert(!(isKill && isDef) && "Kill flag on def"); in ChangeToRegister()
308 IsDef = isDef; in ChangeToRegister()
338 return getReg() == Other.getReg() && isDef() == Other.isDef() && in isIdenticalTo()
406 MO.isDef()); in hash_value()
819 OS << (isDef() ? "implicit-def " : "implicit "); in print()
[all …]
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| H A D | RenameIndependentSubregs.cpp | 186 if (!MO.isDef() && !MO.readsReg()) in findComponents()
196 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) in findComponents()
225 if (!MO.isDef() && !MO.readsReg()) in rewriteOperands()
230 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) in rewriteOperands()
359 if (!MO.isDef()) in computeMainRangesFixFlags()
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| H A D | MIRCanonicalizerPass.cpp | 161 if (!MO.isDef()) in rescheduleCanonically()
177 if (!MO.isDef()) in rescheduleCanonically()
344 if (!MO.isDef() && MO.isKill()) { in doDefKillClear()
349 if (MO.isDef() && MO.isDead()) { in doDefKillClear()
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| H A D | LiveRangeEdit.cpp | 210 if (MO.isDef()) { in foldAsLoad()
315 if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() && in eliminateDeadDef()
341 else if (MO.isDef()) in eliminateDeadDef()
352 (MO.isDef() || TII.isCopyInstr(*MI))) || in eliminateDeadDef()
359 if (MO.isDef()) { in eliminateDeadDef()
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| H A D | LiveRegUnits.cpp | 48 if (MOP.isDef() && MOP.getReg().isPhysical()) in stepBackward()
75 if (MOP.isDef() || MOP.readsReg()) in accumulate()
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| H A D | CriticalAntiDepBreaker.cpp | 284 if (!MO.isDef()) continue; in ScanInstruction()
362 if (RefOper->isDef() && RefOper->isEarlyClobber()) in isNewRegClobberedByRefs()
371 if (!CheckOper.isReg() || !CheckOper.isDef() || in isNewRegClobberedByRefs()
377 if (RefOper->isDef()) in isNewRegClobberedByRefs()
621 if (MO.isDef() && Reg != AntiDepReg) in BreakAntiDependencies()
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| H A D | LivePhysRegs.cpp | 52 if (MOP.isDef()) in removeDefs()
90 if (O->isDef()) { in stepForward()
290 if (!MO->isReg() || !MO->isDef() || MO->isDebug()) in recomputeLivenessFlags()
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| H A D | RegisterScavenging.cpp | 351 if (MO.isDef()) { in scavengeVReg()
440 assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses"); in scavengeFrameVirtualRegsInBlock()
444 if (MO.isDef()) { in scavengeFrameVirtualRegsInBlock()
455 assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses"); in scavengeFrameVirtualRegsInBlock()
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| H A D | VirtRegMap.cpp | 673 if ((MO.readsReg() && (MO.isDef() || MO.isKill())) || in rewrite()
674 (MO.isDef() && subRegLiveThrough(MI, PhysReg))) in rewrite()
677 if (MO.isDef()) { in rewrite()
692 assert(MO.isDef()); in rewrite()
726 if (MO.isDef()) { in rewrite()
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| H A D | MachineStableHash.cpp | 72 MO.isDef()); in stableHashValue()
196 if (!HashVRegs && MO.isReg() && MO.isDef() && MO.getReg().isVirtual()) in stableHashValue()
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| H A D | MachineCSE.cpp | 309 if (!MO.isReg() || !MO.isDef()) in hasLivePhysRegDefUses()
384 if (!MO.isReg() || !MO.isDef()) in PhysRegDefsReach()
628 if (!MO.isReg() || !MO.isDef()) in ProcessBlockCSE()
812 if (MO.isDef()) in isPRECandidate()
871 assert(MI.getOperand(0).isDef() && in ProcessBlockPRE()
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| H A D | TargetSchedule.cpp | 146 if (MO.isReg() && MO.isDef()) in findDefIdx()
162 if (MO.isReg() && MO.readsReg() && !MO.isDef()) in findUseIdx()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegBankSelect.cpp | 153 if (MO.isDef()) in repairReg()
175 if (MO.isDef()) { in repairReg()
247 assert(CurRegBank || MO.isDef()); in getRepairCost()
266 if (MO.isDef()) in getRepairCost()
339 assert((!MI.isPHI() || !MO.isDef()) && "Need split for phi def?"); in tryAvoidingSplit()
342 if (!MO.isDef()) { in tryAvoidingSplit()
366 assert(MI.isTerminator() && MO.isDef() && in tryAvoidingSplit()
773 bool Before = !MO.isDef(); in RepairingPlacement()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineOperand.h | 383 bool isDef() const { in isDef() function
811 LLVM_ABI void ChangeToRegister(Register Reg, bool isDef, bool isImp = false,
842 static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp = false,
849 assert(!(isDead && !isDef) && "Dead flag on non-def");
850 assert(!(isKill && isDef) && "Kill flag on def");
852 Op.IsDef = isDef;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 361 if (!Op.isReg() || !Op.isDef()) in updateDeadsInRange()
487 if (Op.isDef()) { in updateDeadsInRange()
678 assert(MD.isDef()); in split()
735 if (!Op.isReg() || !Op.isDef()) in isPredicable()
773 if (!Op.isReg() || !Op.isDef()) in getReachingDefForPred()
819 if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then)) in canMoveOver()
885 if (!MO.isReg() || !MO.isDef()) in predicateAt()
934 assert(!Op.isDef() && "Not expecting a def"); in renameInRange()
1013 ReferenceMap &Map = Op.isDef() ? Defs : Uses; in predicate()
1014 if (Op.isDef() && Op.isUndef()) { in predicate()
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| H A D | HexagonNewValueJump.cpp | 143 if (!Op.isReg() || !Op.isDef()) in INITIALIZE_PASS_DEPENDENCY()
169 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { in INITIALIZE_PASS_DEPENDENCY()
589 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() && in runOnMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMLatencyMutations.cpp | 763 if (OP.isReg() && OP.isDef() && OP.getReg() == RegID && in modifyMixedWidthFP()
769 if (OP.isReg() && OP.isDef() && OP.getReg() == RegID && in modifyMixedWidthFP()
779 if (OP.isReg() && OP.isDef() && OP.getReg() == RegID && in modifyMixedWidthFP()
815 if (OP.isReg() && OP.isDef() && OP.getReg() >= ARM::S1 && in modifyMixedWidthFP()
824 if (OP.isReg() && OP.isDef() && OP.getReg() >= ARM::S1 && in modifyMixedWidthFP()
834 if (OP.isReg() && OP.isDef() && OP.getReg() >= ARM::D0 && in modifyMixedWidthFP()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiDelaySlotFiller.cpp | 207 if (MO.isDef()) { in delayHasHazard()
236 if (MO.isDef()) in insertDefsUses()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FixupBWInsts.cpp | 256 if (MO.isDef() && TRI->isSuperRegisterEq(OrigDestReg, MO.getReg())) in getSuperRegDestIfDead()
338 if (Op.getReg() != (Op.isDef() ? NewDestReg : NewSrcReg)) in tryReplaceCopy()
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