| /freebsd/contrib/llvm-project/llvm/utils/TableGen/GlobalISel/ |
| H A D | GIMatchDag.cpp | |
| H A D | GIMatchDagOperands.cpp | |
| H A D | GIMatchDagEdge.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveIntervalCalc.cpp | 55 if (!MO.isDef() && !MO.readsReg()) in calculate()
72 if (MO.isDef()) in calculate()
80 if (MO.isDef() && !LI.hasSubRanges()) in calculate()
155 if (!MO.readsReg() || (IsSubRange && MO.isDef())) in extendToUses()
161 if (MO.isDef()) in extendToUses()
173 assert(!MO.isDef() && "Cannot handle PHI def of partial register."); in extendToUses()
181 if (MO.isDef()) in extendToUses()
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| H A D | MachineInstrBundle.cpp | 154 if (MO.isDef()) { in finalizeBundle()
293 if (MO.isDef()) in AnalyzeVirtRegInBundle()
298 if (MO.isDef()) in AnalyzeVirtRegInBundle()
323 if (MO.isDef()) { in AnalyzeVirtRegLanesInBundle()
364 } else if (MO.isDef()) { in AnalyzePhysRegInBundle()
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| H A D | MachineOperand.cpp | 100 if (isDef()) in substPhysReg()
135 if (isDef()) in isRenamable()
273 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp, in ChangeToRegister() argument
287 if (!isDef && MI && MI->isDebugInstr()) in ChangeToRegister()
291 assert(!(isDead && !isDef) && "Dead flag on non-def"); in ChangeToRegister()
292 assert(!(isKill && isDef) && "Kill flag on def"); in ChangeToRegister()
296 IsDef = isDef; in ChangeToRegister()
326 return getReg() == Other.getReg() && isDef() == Other.isDef() && in isIdenticalTo()
393 return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef()); in hash_value()
807 OS << (isDef() ? "implicit-def " : "implicit "); in print()
[all …]
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| H A D | RenameIndependentSubregs.cpp | 180 if (!MO.isDef() && !MO.readsReg()) in findComponents()
190 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) in findComponents()
219 if (!MO.isDef() && !MO.readsReg()) in rewriteOperands()
224 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) in rewriteOperands()
353 if (!MO.isDef()) in computeMainRangesFixFlags()
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| H A D | MIRCanonicalizerPass.cpp | 161 if (!MO.isDef()) in rescheduleCanonically()
177 if (!MO.isDef()) in rescheduleCanonically()
344 if (!MO.isDef() && MO.isKill()) { in doDefKillClear()
349 if (MO.isDef() && MO.isDead()) { in doDefKillClear()
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| H A D | RegisterScavenging.cpp | 352 if (MO.isDef()) { in findSurvivorBackwards()
443 assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses"); in spill()
447 if (MO.isDef()) { in spill()
458 assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses"); in scavengeRegisterBackwards()
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| H A D | LiveRangeEdit.cpp | 214 if (MO.isDef()) { in foldAsLoad()
319 if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() && in eliminateDeadDef()
345 else if (MO.isDef()) in eliminateDeadDef()
356 (MO.isDef() || TII.isCopyInstr(*MI))) || in eliminateDeadDef()
363 if (MO.isDef()) { in eliminateDeadDef()
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| H A D | CriticalAntiDepBreaker.cpp | 282 if (!MO.isDef()) continue; in ScanInstruction()
360 if (RefOper->isDef() && RefOper->isEarlyClobber()) in isNewRegClobberedByRefs()
369 if (!CheckOper.isReg() || !CheckOper.isDef() || in isNewRegClobberedByRefs()
375 if (RefOper->isDef()) in isNewRegClobberedByRefs()
620 if (MO.isDef() && Reg != AntiDepReg) in BreakAntiDependencies()
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| H A D | LiveRegUnits.cpp | 48 if (MOP.isDef() && MOP.getReg().isPhysical()) in stepBackward()
75 if (MOP.isDef() || MOP.readsReg()) in accumulate()
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| H A D | VirtRegMap.cpp | 569 if ((MO.readsReg() && (MO.isDef() || MO.isKill())) || in rewrite()
570 (MO.isDef() && subRegLiveThrough(MI, PhysReg))) in rewrite()
573 if (MO.isDef()) { in rewrite()
588 assert(MO.isDef()); in rewrite()
596 if (MO.isDef()) { in rewrite()
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| H A D | LivePhysRegs.cpp | 52 if (MOP.isDef()) in removeDefs()
90 if (O->isDef()) { in stepForward()
290 if (!MO->isReg() || !MO->isDef() || MO->isDebug()) in recomputeLivenessFlags()
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| H A D | MachineCSE.cpp | 314 if (!MO.isReg() || !MO.isDef()) in hasLivePhysRegDefUses()
391 if (!MO.isReg() || !MO.isDef()) in PhysRegDefsReach()
633 if (!MO.isReg() || !MO.isDef()) in ProcessBlockCSE()
817 if (MO.isDef()) in isPRECandidate()
877 assert(MI.getOperand(0).isDef() && in ProcessBlockPRE()
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| H A D | MachineStableHash.cpp | 73 MO.isDef()); in stableHashValue()
185 if (!HashVRegs && MO.isReg() && MO.isDef() && MO.getReg().isVirtual()) in stableHashValue()
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| H A D | MachineInstr.cpp | 691 if (MO.isDef()) { in isIdenticalTo()
816 if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) in getNumExplicitDefs()
1113 if (!MO.isReg() || !MO.isDef()) in findRegisterDefOperandIdx()
1165 assert(DefMO.isDef() && "DefIdx must be a def operand"); in tieOperands()
1587 if (!Operand.isReg() || Operand.isDef()) in hasComplexRegisterTies()
1641 if (!MO.isReg() || MO.isDef()) in dumprImpl()
1696 if (MO.isReg() && MO.isTied() && !MO.isDef()) in print()
1706 if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) in print()
2085 if (!MO.isReg() || !MO.isDef()) in addRegisterDead()
2129 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg) in clearRegisterDeads()
[all …]
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| H A D | AggressiveAntiDepBreaker.cpp | 233 if (MO.isDef()) in IsImplicitDefUse()
246 if ((MO.isDef() && MI.isRegTiedToUseOperand(i)) || in GetPassthruRegs()
364 if (!MO.isReg() || !MO.isDef()) continue; in PrescanInstruction()
406 if (!MO.isReg() || !MO.isDef()) continue; in PrescanInstruction()
696 if (!Q.second.Operand->isDef() || !Q.second.Operand->isEarlyClobber()) in FindSuitableFreeRegisters()
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| H A D | TargetSchedule.cpp | 149 if (MO.isReg() && MO.isDef()) in findDefIdx()
159 /// is simply the inverse of isDef. Here we consider any readsReg operand to be in findUseIdx()
165 if (MO.isReg() && MO.readsReg() && !MO.isDef()) in findUseIdx()
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| H A D | RegAllocFast.cpp | 1195 if (!MO.isDef()) in setPhysReg()
1208 if (MO.isDef() && MO.isUndef()) { in setPhysReg()
1316 if (MO.isDef() && Reg.isVirtual() && shouldAllocateRegister(Reg)) in findAndSortDefOperandIndexes()
1333 if (MO.isReg() && MO.isDef()) in findAndSortDefOperandIndexes()
1417 if (MO.isDef()) { in allocateInstruction()
1429 if (MO.isDef()) { in allocateInstruction()
1485 if (!MO.isReg() || !MO.isDef()) in allocateInstruction()
1503 if (!MO.isReg() || !MO.isDef()) in allocateInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegBankSelect.cpp | 153 if (MO.isDef()) in repairReg()
175 if (MO.isDef()) { in repairReg()
247 assert(CurRegBank || MO.isDef()); in getRepairCost()
266 if (MO.isDef()) in getRepairCost()
339 assert((!MI.isPHI() || !MO.isDef()) && "Need split for phi def?"); in tryAvoidingSplit()
342 if (!MO.isDef()) { in tryAvoidingSplit()
366 assert(MI.isTerminator() && MO.isDef() && in tryAvoidingSplit()
774 bool Before = !MO.isDef(); in RepairingPlacement()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineOperand.h | 296 /// isDef. Sometimes, if the operand is printed before '=', we don't print
384 bool isDef() const { in isDef() function
806 void ChangeToRegister(Register Reg, bool isDef, bool isImp = false,
837 static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp = false,
844 assert(!(isDead && !isDef) && "Dead flag on non-def");
845 assert(!(isKill && isDef) && "Kill flag on def");
847 Op.IsDef = isDef;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 377 if (!Op.isReg() || !Op.isDef()) in updateDeadsInRange()
504 if (Op.isDef()) { in updateDeadsInRange()
695 assert(MD.isDef()); in split()
752 if (!Op.isReg() || !Op.isDef()) in isPredicable()
790 if (!Op.isReg() || !Op.isDef()) in getReachingDefForPred()
836 if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then)) in canMoveOver()
902 if (!MO.isReg() || !MO.isDef()) in predicateAt()
951 assert(!Op.isDef() && "Not expecting a def"); in renameInRange()
1030 ReferenceMap &Map = Op.isDef() ? Defs : Uses; in predicate()
1031 if (Op.isDef() && Op.isUndef()) { in predicate()
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| H A D | HexagonNewValueJump.cpp | 151 if (!Op.isReg() || !Op.isDef()) in INITIALIZE_PASS_DEPENDENCY()
177 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { in INITIALIZE_PASS_DEPENDENCY()
597 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() && in runOnMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiDelaySlotFiller.cpp | 208 if (MO.isDef()) { in delayHasHazard()
237 if (MO.isDef()) in insertDefsUses()
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