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Searched refs:isBuildVectorAllZeros (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h470 LLVM_ABI bool isBuildVectorAllZeros(const MachineInstr &MI,
H A DGIMatchTableExecutorImpl.h454 if (!isBuildVectorAllZeros(*MI, MRI)) { in executeMatchTable()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp814 if (isBuildVectorAllZeros(MI, MRI) || isBuildVectorAllOnes(MI, MRI)) in matchBuildVectorToDup()
1010 isBuildVectorAllZeros(*MRI.getVRegDef(RHS), MRI)) { in applyLowerVectorFCMP()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp1452 bool llvm::isBuildVectorAllZeros(const MachineInstr &MI, in isBuildVectorAllZeros() function in llvm
1573 return isBuildVectorAllZeros(MI, MRI); in isNullOrNullSplat()
H A DCombinerHelper.cpp3713 return isBuildVectorAllZeros(*VecMI, MRI); in matchPtrAddZero()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp4582 if (IdxVal == 0 && ISD::isBuildVectorAllZeros(Vec.getNode())) { in insert1BitVector()
4623 if (ISD::isBuildVectorAllZeros(Vec.getNode())) { in insert1BitVector()
4985 ISD::isBuildVectorAllZeros(RHS.getNode()); in isTargetCanonicalSelect()
5407 !ISD::isBuildVectorAllZeros(V.getOperand(0).getNode()) && in IsNOT()
5852 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode()); in computeZeroableShuffleElements()
5853 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode()); in computeZeroableShuffleElements()
6303 if (ISD::isBuildVectorAllZeros(Src.getNode())) in getFauxShuffleMask()
7274 if (X86::isZeroNode(Elt) || ISD::isBuildVectorAllZeros(Elt.getNode())) { in EltsFromConsecutiveLoads()
8003 if (ISD::isBuildVectorAllZeros(Op.getNode()) || in LowerBUILD_VECTORvXi1()
8839 if (ISD::isBuildVectorAllZeros(Op.getNode())) in materializeVectorConstant()
[all …]
H A DX86ISelDAGToDAG.cpp822 ISD::isBuildVectorAllZeros(Root->getOperand(0).getNode()))) in IsProfitableToFold()
4942 if (ISD::isBuildVectorAllZeros(SetccOp0.getNode())) in tryVPTESTM()
4946 if (!ISD::isBuildVectorAllZeros(SetccOp1.getNode())) in tryVPTESTM()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp1098 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode()); in computeZeroableShuffleElements()
1099 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode()); in computeZeroableShuffleElements()
2556 } else if (ISD::isBuildVectorAllZeros(SubVec.getNode())) in lowerCONCAT_VECTORS()
4537 return ISD::isBuildVectorAllZeros(Src.getNode()) || in checkBitcastSrcVectorSize()
4600 if (ISD::isBuildVectorAllZeros(SrcN1.getNode()) && EltVT == MVT::i8) in performSETCC_BITCASTCombine()
4610 if (ISD::isBuildVectorAllZeros(SrcN1.getNode()) && EltVT == MVT::i8) in performSETCC_BITCASTCombine()
4615 if (ISD::isBuildVectorAllZeros(SrcN1.getNode()) && in performSETCC_BITCASTCombine()
4629 if (ISD::isBuildVectorAllZeros(SrcN1.getNode()) && EltVT == MVT::i8) in performSETCC_BITCASTCombine()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h112 LLVM_ABI bool isBuildVectorAllZeros(const SDNode *N);
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp8334 bool ZeroN00 = ISD::isBuildVectorAllZeros(N0.getOperand(0).getNode()); in visitOR()
8335 bool ZeroN01 = ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode()); in visitOR()
8336 bool ZeroN10 = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode()); in visitOR()
8337 bool ZeroN11 = ISD::isBuildVectorAllZeros(N1.getOperand(1).getNode()); in visitOR()
13216 bool RHSIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode()); in visitVSELECT()
13221 isAbs = ISD::isBuildVectorAllZeros(N2.getOperand(0).getNode()); in visitVSELECT()
13224 isAbs = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode()); in visitVSELECT()
21738 else if (ISD::isBuildVectorAllZeros(StoredVal.getNode())) in tryStoreMergeOfConstants()
26197 if (N0AnyConst && !N1AnyConst && !ISD::isBuildVectorAllZeros(N0.getNode())) in combineShuffleOfScalars()
26199 if (!N0AnyConst && N1AnyConst && !ISD::isBuildVectorAllZeros(N1.getNode())) in combineShuffleOfScalars()
H A DTargetLowering.cpp882 (isNullConstant(Op1) || ISD::isBuildVectorAllZeros(Op1.getNode()))) in SimplifyMultipleUseDemandedBits()
1767 (isNullConstant(Op1) || ISD::isBuildVectorAllZeros(Op1.getNode()))) in SimplifyDemandedBits()
H A DSelectionDAG.cpp271 bool ISD::isBuildVectorAllZeros(const SDNode *N) { in isBuildVectorAllZeros() function in ISD
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp6973 if (ISD::isBuildVectorAllZeros(Op1.getNode())) in LowerVSETCC()
6975 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) in LowerVSETCC()
6998 if (ISD::isBuildVectorAllZeros(Op0.getNode()) && in LowerVSETCC()
7009 if (ISD::isBuildVectorAllZeros(Op1.getNode()) && in LowerVSETCC()
10307 return (ISD::isBuildVectorAllZeros(N.getNode()) || in isZeroVector()
17228 !ISD::isBuildVectorAllZeros(N0->getOperand(2).getNode())) in PerformVECREDUCE_ADDCombine()
17280 !ISD::isBuildVectorAllZeros(N0->getOperand(2).getNode())) in PerformVECREDUCE_ADDCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp5778 return ISD::isBuildVectorAllZeros(N.getNode()); in isZeroVector()
7819 if (ISD::isBuildVectorAllZeros(Op0.getNode())) { in combineMERGE()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp17146 ISD::isBuildVectorAllZeros(V1.getOperand(0).getNode()) && in PerformDAGCombine()
17152 ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()) && in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp3948 if (ISD::isBuildVectorAllZeros(Op.getNode())) { in lowerBuildVectorOfConstants()
/freebsd/contrib/llvm-project/llvm/include/llvm/Testing/Demangle/
H A DDemangleTestCases.inc15007 {"_ZN4llvm3ISD21isBuildVectorAllZerosEPKNS_6SDNodeE", "llvm::ISD::isBuildVectorAllZeros(llvm::SDNod…