Searched refs:isAssignedRegDep (Results 1 – 14 of 14) sorted by relevance
149 if (S.isAssignedRegDep() && S.getLatency() == 0 && in EmitInstruction()164 if (S.isAssignedRegDep() && S.getLatency() == 0 && in EmitInstruction()
558 if (!I.isAssignedRegDep() || I.getSUnit() != Dst) in restoreLatency()607 if (!I.isAssignedRegDep() || I.getSUnit() != Dst) in changeLatency()623 if (I.isAssignedRegDep() && I.getLatency() == 0 && in getZeroLatency()
1914 if ((Pred.getLatency() == 0 && Pred.isAssignedRegDep()) || in calcStall()
540 (Dep.isAssignedRegDep() && Dep.getReg() == ARM::CPSR) ? 0 : 1); in makeBundleAssumptions()544 Dep.isAssignedRegDep() && Dep.getReg() != ARM::CPSR) { in makeBundleAssumptions()667 if (TII->isPredicated(*SrcMI) && Dep.isAssignedRegDep() && in modifyBypasses()684 if (Dep.isAssignedRegDep() && Dep.getReg() == ARM::CPSR && in modifyBypasses()908 if (Dep.isAssignedRegDep() && Dep.getReg() == ARM::CPSR && in modifyBypasses()
6653 } else if (S.isAssignedRegDep()) { in tooMuchRegisterPressure()6730 if (S.isAssignedRegDep()) { in tooMuchRegisterPressure()
154 if (Pred.isAssignedRegDep()) { in ReleasePredecessors()183 if (Succ.isAssignedRegDep()) { in ScheduleNodeBottomUp()473 if (Pred.isAssignedRegDep()) { in DelayForLiveRegsBottomUp()
132 assert(!Succ.isAssignedRegDep() && in releaseSuccessors()
560 if (Pred.isAssignedRegDep()) { in ReleasePredecessors()774 if (Succ.isAssignedRegDep() && LiveRegDefs[Succ.getReg()] == SU) { in ScheduleNodeBottomUp()843 if (Pred.isAssignedRegDep() && SU == LiveRegGens[Pred.getReg()]){ in UnscheduleNodeBottomUp()889 if (Succ.isAssignedRegDep()) { in UnscheduleNodeBottomUp()903 if (Succ2.isAssignedRegDep() && Succ2.getReg() == Reg && in UnscheduleNodeBottomUp()1358 if (Pred.isAssignedRegDep() && LiveRegDefs[Pred.getReg()] != SU) in DelayForLiveRegsBottomUp()2869 if (!SuccPred.isAssignedRegDep()) in canClobberReachingPhysRegUse()3045 assert(!Edge.isAssignedRegDep()); in PrescheduleNodesWithMultipleUses()
85 if (TRI && isAssignedRegDep()) in dump()714 if (PredDep.isAssignedRegDep() && in WillCreateCycle()
708 if (!PI.getSUnit()->getInstr()->isPseudo() && PI.isAssignedRegDep() && in SchedulingCost()717 if (!SI.getSUnit()->getInstr()->isPseudo() && SI.isAssignedRegDep() && in SchedulingCost()
3608 if (OE.isAssignedRegDep() && !Dst->isBoundaryNode()) in isValidSchedule()
188 bool isAssignedRegDep() const { return Pred.isAssignedRegDep(); } in isAssignedRegDep() function
211 bool isAssignedRegDep() const { return getKind() == Data && Contents.Reg; } in isAssignedRegDep() function
1359 if (D.isAssignedRegDep()) { in computeSUnitReadyCycle()