Searched refs:isAlign4 (Results 1 – 1 of 1) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegBankLegalizeRules.cpp | 624 Predicate isAlign4([](const MachineInstr &MI) -> bool { in RegBankLegalizeRules() local
671 .Any({{{UniB256, UniP1}, isAlign4 && isUL}, {{SgprB256}, {SgprP1}}}) in RegBankLegalizeRules()
672 .Any({{{UniB512, UniP1}, isAlign4 && isUL}, {{SgprB512}, {SgprP1}}}) in RegBankLegalizeRules()
673 .Any({{{UniB32, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB32}, {SgprP1}}}) in RegBankLegalizeRules()
674 .Any({{{UniB256, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB256}, {VgprP1}, SplitLoad}}) in RegBankLegalizeRules()
675 .Any({{{UniB512, UniP1}, !isAlign4 || !isUL}, {{UniInVgprB512}, {VgprP1}, SplitLoad}}) in RegBankLegalizeRules()
678 .Any({{{UniB32, UniP3}, isAlign4 && isUL}, {{SgprB32}, {SgprP3}}}) in RegBankLegalizeRules()
679 .Any({{{UniB32, UniP3}, !isAlign4 || !isUL}, {{UniInVgprB32}, {VgprP3}}}) in RegBankLegalizeRules()
683 .Any({{{UniB32, UniP4}, isAlign4 && isUL}, {{SgprB32}, {SgprP4}}}) in RegBankLegalizeRules()
685 ….Any({{{UniB96, UniP4}, isAlign4 && !isAlign16 && isUL}, {{SgprB96}, {SgprP4}, SplitLoad}}, !hasUn… in RegBankLegalizeRules()
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