| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 597 bool isAdd = true; in EncodeAddrModeOpValues() local
602 isAdd = false; in EncodeAddrModeOpValues()
608 isAdd = false; in EncodeAddrModeOpValues()
612 return isAdd; in EncodeAddrModeOpValues()
978 bool isAdd = true; in getAddrModeImm12OpValue() local
984 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI); in getAddrModeImm12OpValue()
989 isAdd = false; // 'U' bit is set as part of the fixup. in getAddrModeImm12OpValue()
995 isAdd = false; // 'U' bit is set as part of the fixup. in getAddrModeImm12OpValue()
1009 isAdd = false; in getAddrModeImm12OpValue()
1012 isAdd = false; in getAddrModeImm12OpValue()
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| H A D | ARMAsmBackend.cpp | 512 bool isAdd = true; in adjustFixupValue() local
515 isAdd = false; in adjustFixupValue()
521 Value |= isAdd << 23; in adjustFixupValue()
781 bool isAdd = true; in adjustFixupValue() local
784 isAdd = false; in adjustFixupValue()
792 return Value | (isAdd << 23); in adjustFixupValue()
801 bool isAdd = true; in adjustFixupValue() local
804 isAdd = false; in adjustFixupValue()
812 Value |= isAdd << 23; in adjustFixupValue()
828 bool isAdd = true; in adjustFixupValue() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo16Instr.td | 59 let isCommutable = 1, isAdd = 1 in
64 let isCommutable = 1, isAdd = 1 in
69 let isAdd = 1 in
94 let isAdd = 1, Pattern = [(set mGPR:$rz, (add mGPR:$rZ, oimm8:$imm8))] in
103 let isAdd = 1 in
107 let isAdd = 1 in
117 let isAdd = 1 in
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| H A D | CSKYInstrInfo.td | 524 let isAdd = 1 in
548 let isAdd = 1 in
606 let isCommutable = 1, isAdd = 1 in
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | InstrDocsEmitter.cpp | 120 FLAG(isAdd) in EmitInstrDocs()
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| H A D | InstrInfoEmitter.cpp | 1145 if (Inst.isAdd) in emitRecord()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenInstruction.h | 251 bool isAdd : 1; variable
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| H A D | CodeGenInstruction.cpp | 445 isAdd = R->getValueAsBit("isAdd"); in CodeGenInstruction()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 280 bool isAdd() const { return Flags & (1ULL << MCID::Add); } in isAdd() function
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | GenericMachineInstrs.h | 432 bool isAdd() const { in isAdd() function
443 bool isSub() const { return !isAdd(); } in isSub()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 900 bool isAdd; member
3087 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); in addAM3OffsetOperands()
3333 bool isAdd = Imm >= 0; in addPostIdxImm8Operands() local
3335 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; in addPostIdxImm8Operands()
3344 bool isAdd = Imm >= 0; in addPostIdxImm8s4Operands() local
3347 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; in addPostIdxImm8s4Operands()
3354 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd)); in addPostIdxRegOperands()
3362 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; in addPostIdxRegShiftedOperands()
3911 CreatePostIdxReg(MCRegister Reg, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg() argument
3915 Op->PostIdxReg.isAdd = isAdd; in CreatePostIdxReg()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.td | 2943 // {12} isAdd
2961 // {12} isAdd
3053 // {12} isAdd
3072 // {12} isAdd
3089 // {12} isAdd
3108 // {12} isAdd
3225 // {12} isAdd
3243 // {12} isAdd
3390 // {12} isAdd
3409 // {12} isAdd
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| H A D | ARMInstrFormats.td | 806 // {12} isAdd
824 // {12} isAdd
845 // {12} isAdd
898 // {8} isAdd
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| H A D | ARMInstrThumb.td | 965 let isAdd = 1 in {
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| H A D | ARMInstrThumb2.td | 2430 let isAdd = 1 in
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 437 if (DI->getDesc().isAdd()) { in findInductionRegister()
1662 if (DI->getDesc().isAdd()) { in fixupInductionVariable()
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| H A D | HexagonDepInstrInfo.td | 220 let isAdd = 1;
236 let isAdd = 1;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUIGroupLP.cpp | 1351 auto isAdd = [](unsigned Opc) { return Opc == AMDGPU::V_ADD_F32_e32; }; in analyzeDAG() local
1376 if (isAdd(Opc)) in analyzeDAG()
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| H A D | VOP2Instructions.td | 919 let SubtargetPredicate = HasAddNoCarryInsts, isReMaterializable = 1, isAdd = 1 in {
923 let isAdd = 1 in {
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| H A D | SOPInstructions.td | 618 let isCommutable = 1, isAdd = 1 in {
623 } // End isCommutable = 1, isAdd = 1
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| H A D | SIRegisterInfo.cpp | 892 assert(MI.getDesc().isAdd()); in isFIPlusImmOrVGPR()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | Target.td | 644 bit isAdd = false; // Is this instruction an add instruction?
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 49396 auto combineMulShlAddOrSub = [&](int Mult, int Shift, bool isAdd) { in combineMulSpecial() argument
49401 Result = DAG.getNode(isAdd ? ISD::ADD : ISD::SUB, DL, VT, Result, in combineMulSpecial()
49406 auto combineMulMulAddOrSub = [&](int Mul1, int Mul2, bool isAdd) { in combineMulSpecial() argument
49411 Result = DAG.getNode(isAdd ? ISD::ADD : ISD::SUB, DL, VT, Result, in combineMulSpecial()
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