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Searched refs:isAGPRClass (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNPreRAOptimizations.cpp104 bool IsAGPRDst = TRI->isAGPRClass(MRI->getRegClass(Reg)); in processReg()
126 bool IsAGPRSrc = TRI->isAGPRClass(MRI->getRegClass(SrcReg)); in processReg()
257 (ST.hasGFX90AInsts() || !TRI->isAGPRClass(RC))) in run()
H A DAMDGPURewriteAGPRCopyMFMA.cpp116 if (!TRI.isAGPRClass(AssignedRC)) in run()
H A DSIRegisterInfo.h250 static bool isAGPRClass(const TargetRegisterClass *RC) { in isAGPRClass() function
H A DGCNRegPressure.cpp41 return STI->isSGPRClass(RC) ? SGPR : (STI->isAGPRClass(RC) ? AGPR : VGPR); in getRegKind()
414 SRI->isAGPRClass(RC) ? RP.getAGPRNum() : RP.getArchVGPRNum(); in isSaveBeneficial()
H A DSIRegisterInfo.cpp463 if (ST.hasMAIInsts() && (isVGPRClass(RC) || isAGPRClass(RC))) { in getLargestLegalSuperClass()
760 if (RC->isBaseClass() && isAGPRClass(RC)) { in getReservedRegs()
1176 if (isAGPRClass(RC) && !ST.hasGFX90AInsts()) in getCrossCopyRegClass()
1592 const bool IsAGPR = !ST.hasGFX90AInsts() && isAGPRClass(RC); in buildSpillLoadStore()
3722 return RC && isAGPRClass(RC); in isAGPR()
3996 if (isAGPRClass(&RC)) in isProperlyAlignedRC()
4016 if (isAGPRClass(RC)) in getProperlyAlignedRC()
H A DSIFixSGPRCopies.cpp324 bool IsAGPR = TRI->isAGPRClass(DstRC); in foldVGPRCopyIntoRegSequence()
836 if (HasUses && AllAGPRUses && !TRI->isAGPRClass(RC0)) { in processPHINode()
H A DSIInstrInfo.cpp1082 if (RI.isAGPRClass(RC)) { in copyPhysReg()
1083 if (ST.hasGFX90AInsts() && RI.isAGPRClass(SrcRC)) in copyPhysReg()
1090 } else if (RI.hasVGPRs(RC) && RI.isAGPRClass(SrcRC)) { in copyPhysReg()
1389 if (RI.isAGPRClass(DstRC)) in getMovOpcode()
1724 return TRI.isAGPRClass(RC) ? getAGPRSpillSaveOpcode(Size) in getVectorRegSpillSaveOpcode()
1952 return TRI.isAGPRClass(RC) ? getAGPRSpillRestoreOpcode(Size) in getVectorRegSpillRestoreOpcode()
2201 bool IsAGPR = SIRegisterInfo::isAGPRClass(RI.getPhysRegBaseClass(Dst)); in expandPostRAPseudo()
6918 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
6922 VRC = RI.isAGPRClass(getOpRegClass(MI, 0)) in legalizeOperands()
8945 if (RI.isAGPRClass(SrcRC)) { in getDestEquivalentVGPRClass()
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H A DSIFoldOperands.cpp1808 if (!TRI->isAGPRClass(DefRC)) in foldCopyToAGPRRegSequence()
H A DSILoadStoreOptimizer.cpp1937 return TRI->isAGPRClass(getDataRegClass(*CI.I)) in getTargetRegisterClass()
H A DAMDGPURegisterBankInfo.cpp304 return TRI->isAGPRClass(&RC) ? AMDGPU::AGPRRegBank : AMDGPU::VGPRRegBank; in getRegBankFromRegClass()
H A DSIISelLowering.cpp16506 else if (SIRegisterInfo::isAGPRClass(RC)) in getRegForInlineAsmConstraint()