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Searched refs:iommu (Results 1 – 25 of 218) sorted by relevance

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/freebsd/sys/arm64/iommu/
H A Diommu.c77 struct iommu_unit *iommu; member
86 struct iommu_unit *iommu; in iommu_domain_unmap_buf() local
89 iommu = iodom->iommu; in iommu_domain_unmap_buf()
90 error = IOMMU_UNMAP(iommu->dev, iodom, entry->start, entry->end - in iommu_domain_unmap_buf()
99 struct iommu_unit *iommu; in iommu_domain_map_buf() local
113 iommu = iodom->iommu; in iommu_domain_map_buf()
114 error = IOMMU_MAP(iommu->dev, iodom, va, ma, entry->end - in iommu_domain_map_buf()
125 iommu_domain_alloc(struct iommu_unit *iommu) in iommu_domain_alloc() argument
129 iodom = IOMMU_DOMAIN_ALLOC(iommu->dev, iommu); in iommu_domain_alloc()
135 iommu_domain_init(iommu, iodom, &domain_map_ops); in iommu_domain_alloc()
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H A Dsmmu_fdt.c81 struct iommu_unit *iommu; in smmu_fdt_attach() local
162 iommu = &unit->iommu; in smmu_fdt_attach()
163 iommu->dev = dev; in smmu_fdt_attach()
170 err = iommu_register(iommu); in smmu_fdt_attach()
H A Diommu_if.m44 #include <dev/iommu/iommu.h>
52 INTERFACE iommu;
55 # Check if the iommu controller dev is responsible to serve traffic
90 struct iommu_unit *iommu;
117 # Allocate a new iommu context.
127 # Initialize the new iommu context.
135 # Free the iommu context.
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dpci-iommu.txt26 Documentation/devicetree/bindings/iommu/iommu.txt.
35 - iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
39 (rid-base,iommu,iommu-base,length).
42 the listed IOMMU, with the IOMMU specifier (r - rid-base + iommu-base).
44 - iommu-map-mask: A mask to be applied to each Requester ID prior to being
45 mapped to an IOMMU specifier per the iommu-map property.
55 iommu: iommu@a {
57 compatible = "vendor,some-iommu";
58 #iommu-cells = <1>;
70 iommu-map = <0x0 &iommu 0x0 0x10000>;
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/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Dqcom,iommu.txt12 "qcom,msm8916-iommu"
13 "qcom,msm8953-iommu"
15 Followed by "qcom,msm-iommu-v1".
28 - #iommu-cells : Must be 1. Index identifies the context-bank #.
30 - ranges : Base address and size of the iommu context banks.
32 - qcom,iommu-secure-id : secure-id.
38 - "qcom,msm-iommu-v1-ns" : non-secure context bank
39 - "qcom,msm-iommu-v1-sec" : secure context bank
40 - reg : Base address and size of context bank within the iommu
46 be only specified if the iommu requires configuration
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H A Dti,omap-iommu.txt5 "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
6 "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
7 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
8 "ti,dra7-iommu" for DRA7xx IOMMU instances
12 - #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices,
16 Documentation/devicetree/bindings/iommu/iommu.txt
21 - ti,iommu-bus-err-back : Indicates the IOMMU instance supports throwing
34 #iommu-cells = <0>;
35 compatible = "ti,omap2-iommu";
44 compatible = "ti,dra7-dsp-iommu";
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H A Drockchip,iommu.txt4 A Rockchip DRM iommu translates io virtual addresses to physical addresses for
9 - compatible : Should be "rockchip,iommu"
13 - #iommu-cells : Should be <0>. This indicates the iommu is a
16 Documentation/devicetree/bindings/iommu/iommu.txt
30 vopl_mmu: iommu@ff940300 {
31 compatible = "rockchip,iommu";
37 #iommu-cells = <0>;
H A Dmsm,iommu-v0.txt9 - compatible: Must contain "qcom,apq8064-iommu".
15 - #iommu-cells: The number of cells needed to specify the stream id. This
27 required for iommu's register accesses.
29 required by iommu for bus accesses.
36 A single master device can be connected to more than one iommu
37 and multiple contexts in each of the iommu. So multiple entries
41 Example: mdp iommu and its bus master
43 mdp_port0: iommu@7500000 {
44 compatible = "qcom,apq8064-iommu";
45 #iommu-cells = <1>;
H A Diommu.txt40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
46 - #iommu-cells = <0>: Single master IOMMU devices are not configurable and
52 - #iommu-cells = <1>: Multiple master IOMMU devices may need to be configured
56 - #iommu-cells = <4>: Some IOMMU devices allow the DMA window for masters to
132 iommu {
133 #iommu-cells = <0>;
137 iommus = <&{/iommu}>;
144 iommu {
153 #iommu-cells = <0>;
159 iommus = <&{/iommu}>;
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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dmediatek-vcodec.txt26 argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
52 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
53 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
54 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
55 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
56 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
57 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
58 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
59 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
93 iommus = <&iommu M4U_PORT_VENC_RCPU>,
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H A Dmediatek-mdp.txt28 argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
39 iommus = <&iommu M4U_PORT_MDP_RDMA0>;
49 iommus = <&iommu M4U_PORT_MDP_RDMA1>;
78 iommus = <&iommu M4U_PORT_MDP_WDMA>;
86 iommus = <&iommu M4U_PORT_MDP_WROT0>;
94 iommus = <&iommu M4U_PORT_MDP_WROT1>;
/freebsd/sys/contrib/device-tree/Bindings/virtio/
H A Dmmio.txt11 Required properties for virtio-iommu:
13 - #iommu-cells: When the node corresponds to a virtio-iommu device, it is
14 linked to DMA masters using the "iommus" or "iommu-map"
15 properties [1][2]. #iommu-cells specifies the size of the
16 "iommus" property. For virtio-iommu #iommu-cells must be
22 have an "iommus" property [1]. Since virtio-iommu itself
24 node cannot have both an "#iommu-cells" and an "iommus"
38 viommu: iommu@3100 {
43 #iommu-cells = <1>
46 [1] Documentation/devicetree/bindings/iommu/iommu.txt
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H A Diommu.txt3 When virtio-iommu uses the PCI transport, its programming interface is
6 masters. Therefore, the PCI root complex that hosts the virtio-iommu
11 - compatible: Should be "virtio,pci-iommu"
18 - #iommu-cells: Each platform DMA master managed by the IOMMU is assigned
20 For virtio-iommu, #iommu-cells must be 1.
25 virtio-iommu node doesn't have an "iommus" property, and is omitted from
26 the iommu-map property of the root complex.
35 iommu0: iommu@0008 {
36 compatible = "virtio,pci-iommu";
38 #iommu-cells = <1>;
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/freebsd/sys/x86/iommu/
H A Damd_cmd.c81 amdiommu_enable_qi_intr(struct iommu_unit *iommu) in amdiommu_enable_qi_intr() argument
85 unit = IOMMU2AMD(iommu); in amdiommu_enable_qi_intr()
94 amdiommu_disable_qi_intr(struct iommu_unit *iommu) in amdiommu_disable_qi_intr() argument
98 unit = IOMMU2AMD(iommu); in amdiommu_disable_qi_intr()
105 amdiommu_cmd_advance_tail(struct iommu_unit *iommu) in amdiommu_cmd_advance_tail() argument
109 unit = IOMMU2AMD(iommu); in amdiommu_cmd_advance_tail()
115 amdiommu_cmd_ensure(struct iommu_unit *iommu, int descr_count) in amdiommu_cmd_ensure() argument
121 unit = IOMMU2AMD(iommu); in amdiommu_cmd_ensure()
147 amdiommu_cmd_advance_tail(iommu); in amdiommu_cmd_ensure()
170 amdiommu_cmd_emit_wait_descr(struct iommu_unit *iommu, uint32_t seq, in amdiommu_cmd_emit_wait_descr() argument
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H A Dintel_fault.c96 printf("DMAR%d: Invalidation timed out\n", unit->iommu.unit); in dmar_fault_intr_clear()
101 unit->iommu.unit); in dmar_fault_intr_clear()
106 unit->iommu.unit); in dmar_fault_intr_clear()
110 printf("DMAR%d: Advanced pending fault\n", unit->iommu.unit); in dmar_fault_intr_clear()
114 printf("DMAR%d: Advanced fault overflow\n", unit->iommu.unit); in dmar_fault_intr_clear()
176 printf("DMAR%d: Fault Overflow\n", unit->iommu.unit); in dmar_fault_intr()
208 printf("DMAR%d: ", unit->iommu.unit); in dmar_fault_task()
276 "dmar%d fault taskq", unit->iommu.unit); in dmar_init_fault_log()
279 dmar_disable_fault_intr(&unit->iommu); in dmar_init_fault_log()
281 dmar_enable_fault_intr(&unit->iommu); in dmar_init_fault_log()
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H A Dintel_qi.c88 dmar_qi_advance_tail(struct iommu_unit *iommu) in dmar_qi_advance_tail() argument
92 unit = IOMMU2DMAR(iommu); in dmar_qi_advance_tail()
98 dmar_qi_ensure(struct iommu_unit *iommu, int descr_count) in dmar_qi_ensure() argument
104 unit = IOMMU2DMAR(iommu); in dmar_qi_ensure()
169 dmar_qi_emit_wait_descr(struct iommu_unit *iommu, uint32_t seq, bool intr, in dmar_qi_emit_wait_descr() argument
174 unit = IOMMU2DMAR(iommu); in dmar_qi_emit_wait_descr()
298 unit->iommu.unit)); in dmar_qi_intr()
383 dmar_fini_qi_helper(struct iommu_unit *iommu) in dmar_fini_qi_helper() argument
385 dmar_disable_qi_intr(iommu); in dmar_fini_qi_helper()
386 dmar_disable_qi(IOMMU2DMAR(iommu)); in dmar_fini_qi_helper()
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H A Damd_drv.c241 if (bus_get_domain(sc->iommu.dev, &dom) == 0) in amdiommu_create_dev_tbl()
315 msi_count = pci_msi_count(sc->iommu.dev); in amdiommu_setup_intr()
316 msix_count = pci_msix_count(sc->iommu.dev); in amdiommu_setup_intr()
318 device_printf(sc->iommu.dev, "needs MSI-class intr\n"); in amdiommu_setup_intr()
329 sc->msix_table = bus_alloc_resource_any(sc->iommu.dev, in amdiommu_setup_intr()
336 sc->msix_pba = bus_alloc_resource_any(sc->iommu.dev, in amdiommu_setup_intr()
340 bus_release_resource(sc->iommu.dev, in amdiommu_setup_intr()
351 error = pci_alloc_msix(sc->iommu.dev, &msix_count); in amdiommu_setup_intr()
356 error = pci_alloc_msi(sc->iommu.dev, &msi_count); in amdiommu_setup_intr()
361 device_printf(sc->iommu.dev, in amdiommu_setup_intr()
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H A Dintel_drv.c269 iommu_fini_busdma(&unit->iommu); in dmar_release_resources()
290 sysctl_ctx_free(&unit->iommu.sysctl_ctx); in dmar_release_resources()
370 unit->iommu.unit = device_get_unit(dev); in dmar_attach()
371 unit->iommu.dev = dev; in dmar_attach()
372 sysctl_ctx_init(&unit->iommu.sysctl_ctx); in dmar_attach()
373 dmaru = dmar_find_by_index(unit->iommu.unit); in dmar_attach()
383 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
412 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
432 dmar_devs[unit->iommu.unit] = NULL; in dmar_attach()
441 mtx_init(&unit->iommu.lock, "dmarhw", NULL, MTX_DEF); in dmar_attach()
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H A Dintel_ctx.c163 unit->iommu.unit, busno, pci_get_slot(ctx->context.tag->owner), in ctx_id_entry_init()
245 domain->iodom.iommu->unit, bus, slot, func, in domain_init_rmrr()
257 domain->iodom.iommu->unit, start, end); in domain_init_rmrr()
277 IOMMU_LOCK(domain->iodom.iommu); in domain_init_rmrr()
280 IOMMU_UNLOCK(domain->iodom.iommu); in domain_init_rmrr()
288 domain->iodom.iommu->unit, start, end, in domain_init_rmrr()
442 IOMMU_ASSERT_LOCKED(domain->iodom.iommu); in dmar_ctx_link()
457 IOMMU_ASSERT_LOCKED(domain->iodom.iommu); in dmar_ctx_unlink()
527 ("iommu%d pci%d:%d:%d get_ctx for buswide", dmar->iommu.unit, bus, in dmar_get_ctx_for_dev1()
584 dmar->iommu.unit, dmar->segment, bus, slot, in dmar_get_ctx_for_dev1()
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/freebsd/sys/conf/
H A Dfiles.x86156 dev/iommu/busdma_iommu.c optional acpi iommu pci
157 dev/iommu/iommu_gas.c optional acpi iommu pci
347 x86/iommu/amd_cmd.c optional acpi iommu pci
348 x86/iommu/amd_ctx.c optional acpi iommu pci
349 x86/iommu/amd_drv.c optional acpi iommu pci
350 x86/iommu/amd_event.c optional acpi iommu pci
351 x86/iommu/amd_idpgtbl.c optional acpi iommu pci
352 x86/iommu/amd_intrmap.c optional acpi iommu pci
353 x86/iommu/intel_ctx.c optional acpi iommu pci
354 x86/iommu/intel_drv.c optional acpi iommu pci
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/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8173.dtsi576 iommu: iommu@10205000 { label
585 #iommu-cells = <1>;
1016 iommus = <&iommu M4U_PORT_MDP_RDMA0>;
1026 iommus = <&iommu M4U_PORT_MDP_RDMA1>;
1055 iommus = <&iommu M4U_PORT_MDP_WDMA>;
1063 iommus = <&iommu M4U_PORT_MDP_WROT0>;
1071 iommus = <&iommu M4U_PORT_MDP_WROT1>;
1080 iommus = <&iommu M4U_PORT_DISP_OVL0>;
1090 iommus = <&iommu M4U_PORT_DISP_OVL1>;
1100 iommus = <&iommu M4U_PORT_DISP_RDMA0>;
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/freebsd/sys/contrib/device-tree/Bindings/misc/
H A Dfsl,qoriq-mc.txt21 between ICIDs and IOMMUs, so an iommu-map property is used to define
26 Documentation/devicetree/bindings/iommu/iommu.txt.
29 Documentation/devicetree/bindings/iommu/arm,smmu.yaml.
117 - iommu-map: Maps an ICID to an IOMMU and associated iommu-specifier
121 (icid-base,iommu,iommu-base,length).
124 associated with the listed IOMMU, with the iommu-specifier
125 (i - icid-base + iommu-base).
151 smmu: iommu@5000000 {
153 #iommu-cells = <1>;
173 iommu-map = <23 &smmu 23 41>;
/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Dt600x-die0.dtsi56 sio_dart_0: iommu@39b004000 {
61 #iommu-cells = <1>;
65 sio_dart_1: iommu@39b008000 {
70 #iommu-cells = <1>;
220 pcie0_dart_0: iommu@581008000 {
223 #iommu-cells = <1>;
229 pcie0_dart_1: iommu@582008000 {
232 #iommu-cells = <1>;
238 pcie0_dart_2: iommu@583008000 {
241 #iommu-cells = <1>;
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/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dr8a77950.dtsi87 ipmmu_mp1: iommu@ec680000 {
92 #iommu-cells = <1>;
95 ipmmu_sy: iommu@e7730000 {
100 #iommu-cells = <1>;
103 /delete-node/ iommu@fd950000;
104 /delete-node/ iommu@fd960000;
105 /delete-node/ iommu@fd970000;
106 /delete-node/ iommu@febe0000;
107 /delete-node/ iommu@fe980000;
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dp5020si-post.dtsi66 fsl,iommu-parent = <&pamu0>;
95 fsl,iommu-parent = <&pamu0>;
124 fsl,iommu-parent = <&pamu0>;
153 fsl,iommu-parent = <&pamu0>;
178 fsl,iommu-parent = <&pamu0>;
307 iommu@20000 {
382 fsl,iommu-parent = <&pamu0>;
388 fsl,iommu-parent = <&pamu0>;
400 fsl,iommu-parent = <&pamu1>;
413 fsl,iommu-parent = <&pamu1>;
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