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Searched refs:imm4 (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLBTInstrFormats.td52 : LAInst<(outs), (ins GPR:$rj, uimm4:$imm4),
53 deriveInsnMnemonic<NAME>.ret, "$rj, $imm4"> {
54 bits<4> imm4;
58 let Inst{13-10} = imm4;
65 : LAInst<(outs GPR:$rd), (ins uimm4:$imm4),
66 deriveInsnMnemonic<NAME>.ret, "$rd, $imm4"> {
67 bits<4> imm4;
71 let Inst{13-10} = imm4;
91 : LAInst<(outs), (ins GPR:$rj, uimm5:$imm5, uimm4:$imm4),
92 deriveInsnMnemonic<NAME>.ret, "$rj, $imm5, $imm4"> {
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H A DLoongArchLASXInstrFormats.td175 bits<4> imm4;
180 let Inst{13-10} = imm4;
189 bits<4> imm4;
194 let Inst{13-10} = imm4;
203 bits<4> imm4;
208 let Inst{13-10} = imm4;
312 bits<4> imm4;
318 let Inst{21-18} = imm4;
H A DLoongArchLSXInstrFormats.td203 bits<4> imm4;
208 let Inst{13-10} = imm4;
217 bits<4> imm4;
222 let Inst{13-10} = imm4;
231 bits<4> imm4;
236 let Inst{13-10} = imm4;
357 bits<4> imm4;
363 let Inst{21-18} = imm4;
H A DLoongArchLASXInstrInfo.td88 : Fmt2RI4_XXI<op, (outs LASX256:$xd), (ins LASX256:$xj, ImmOpnd:$imm4),
89 "$xd, $xj, $imm4">;
92 : Fmt2RI4_XRI<op, (outs LASX256:$xd), (ins GPR:$rj, ImmOpnd:$imm4),
93 "$xd, $rj, $imm4">;
96 : Fmt2RI4_RXI<op, (outs GPR:$rd), (ins LASX256:$xj, ImmOpnd:$imm4),
97 "$rd, $xj, $imm4">;
124 (ins LASX256:$xd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm4),
125 "$xd, $rj, $imm8, $imm4">;
162 : Fmt2RI4_XXI<op, (outs LASX256:$dst), (ins LASX256:$xd, LASX256:$xj, ImmOpnd:$imm4),
163 "$xd, $xj, $imm4">;
H A DLoongArchLSXInstrInfo.td300 : Fmt2RI4_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm4),
301 "$vd, $vj, $imm4">;
304 : Fmt2RI4_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm4),
305 "$rd, $vj, $imm4">;
337 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm4),
338 "$vd, $rj, $imm8, $imm4">;
365 : Fmt2RI4_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm4),
366 "$vd, $rj, $imm4">;
369 : Fmt2RI4_VVI<op, (outs LSX128:$dst), (ins LSX128:$vd, LSX128:$vj, ImmOpnd:$imm4),
370 "$vd, $vj, $imm4">;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZimop.td25 class RVInstRMoprr<bits<4> imm4, bits<3> imm3, bits<3> funct3, RISCVOpcode opcode,
28 let Inst{31} = imm4{3};
30 let Inst{29-28} = imm4{2-1};
32 let Inst{25} = imm4{0};
51 class RVMoprr<bits<4> imm4, bits<3> imm3, bits<3> funct3,
53 : RVInstRMoprr<imm4, imm3, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16InstrFormats.td270 // Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
280 bits<4> imm4;
288 let Inst{3-0} = imm4;
428 // <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>
479 // <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>
503 // <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0>
581 // <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0>
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DSVEInstrFormats.td1172 : I<(outs GPR64:$Rd), (ins sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
1173 asm, "\t$Rd, $pattern, mul $imm4",
1177 bits<4> imm4;
1182 let Inst{19-16} = imm4;
1212 : I<(outs zprty:$Zdn), (ins zprty:$_Zdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
1213 asm, "\t$Zdn, $pattern, mul $imm4",
1218 bits<4> imm4;
1223 let Inst{19-16} = imm4;
1245 def : Pat<(vt (op (vt zprty:$Zn), (sve_pred_enum:$pattern), (sve_incdec_imm:$imm4))),
1246 (!cast<Instruction>(NAME) $Zn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4)>;
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H A DSMEInstrFormats.td1108 : I<outs, ins, opcodestr, "\t$ZAt[$Rv, $imm4], [$Rn, $offset, mul vl]", "",
1113 bits<4> imm4;
1121 let Inst{3-0} = imm4;
1128 sme_elm_idx0_15:$imm4, GPR64sp:$Rn,
1135 sme_elm_idx0_15:$imm4, GPR64sp:$Rn,
1140 def : InstAlias<opcodestr # "\t$ZAt[$Rv, $imm4], [$Rn]",
1142 MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm4, GPR64sp:$Rn, 0), 1>;
1150 def : InstAlias<opcodestr # "\t$ZAt[$Rv, $imm4], [$Rn]",
1152 MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm4, GPR64sp:$Rn, 0), 1>;
1155 (ins MatrixIndexGPR32Op12_15:$idx, sme_elm_idx0_15:$imm4,
[all …]
H A DAArch64InstrFormats.td3221 isSub, 0, GPR64sp, asm_inst, "\t$Rd, $Rn, $imm6, $imm4",
3222 (ins GPR64sp:$Rn, uimm6s16:$imm6, imm0_15:$imm4),
3223 (set GPR64sp:$Rd, (OpNode GPR64sp:$Rn, imm0_63:$imm6, imm0_15:$imm4))> {
3225 bits<4> imm4;
3230 let Inst{13-10} = imm4;
8259 class BaseSIMDMov<bit Q, string size, bits<4> imm4, RegisterClass regtype,
8264 let Inst{14-11} = imm4;
12834 bits<9> simm; // signed immediate encoded in imm9=Rt2:imm4
H A DAArch64InstrInfo.td3024 def : Pat<(int_aarch64_addg (am_indexedu6s128 GPR64sp:$Rn, uimm6s16:$imm6), imm0_15:$imm4),
3025 (ADDG GPR64sp:$Rn, imm0_63:$imm6, imm0_15:$imm4)>;
3071 : Pseudo<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, uimm6s16:$imm6, GPR64sp:$Rm, imm0_15:$imm4), []>,
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrFormats.td66 bits<4> imm4;
68 let Inst{23-20} = imm4;
H A DXtensaInstrInfo.td790 let imm4 = 0x4;
799 let imm4 = 0x0;
/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DRISCV.cpp365 uint16_t imm4 = extractBits(val, 4, 4) << 11; in relocate() local
372 insn |= imm11 | imm4 | imm9_8 | imm10 | imm6 | imm7 | imm3_1 | imm5; in relocate()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrFormatsF1.td162 let Inst{24 - 21} = regs{3-0}; //imm4
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/MIPS/
H A DEmulateInstructionMIPS.cpp1457 const uint32_t imm4 = insn.getOperand(2).getImm(); in Emulate_ADDIUS5() local
1471 result = src_opd_val + imm4; in Emulate_ADDIUS5()
1477 context.SetRegisterPlusOffset(*reg_info_sp, imm4); in Emulate_ADDIUS5()
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp1407 uint32_t imm4 = Bits32(opcode, 19, 16); in EmulateMOVRdImm() local
1411 imm32 = (imm4 << 12) | (i << 11) | (imm3 << 8) | imm8; in EmulateMOVRdImm()
1436 uint32_t imm4 = Bits32(opcode, 19, 16); in EmulateMOVRdImm() local
1438 imm32 = (imm4 << 12) | imm12; in EmulateMOVRdImm()