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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZicbo.td34 let imm12 = optype;
40 : RVInstS<0b110, OPC_OP_IMM, (outs), (ins GPRMem:$rs1, simm12_lsb00000:$imm12),
41 opcodestr, "${imm12}(${rs1})"> {
73 def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12),
75 (PREFETCH_I GPR:$rs1, simm12_lsb00000:$imm12)>;
76 def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12),
78 (PREFETCH_R GPR:$rs1, simm12_lsb00000:$imm12)>;
79 def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12),
81 (PREFETCH_W GPR:$rs1, simm12_lsb00000:$imm12)>;
H A DRISCVInstrFormats.td437 bits<12> imm12;
439 let Inst{31-20} = imm12;
461 class RVInstIUnary<bits<12> imm12, bits<3> funct3, RISCVOpcode opcode,
464 let Inst{31-20} = imm12;
470 bits<12> imm12;
474 let Inst{31-25} = imm12{11-5};
478 let Inst{11-7} = imm12{4-0};
485 bits<12> imm12;
489 let Inst{31} = imm12{11};
490 let Inst{30-25} = imm12{9-4};
[all …]
H A DRISCVInstrInfo.td620 (ins GPR:$rs1, GPR:$rs2, bare_simm13_lsb0:$imm12),
621 opcodestr, "$rs1, $rs2, $imm12">,
632 : RVInstI<funct3, OPC_LOAD, (outs rty:$rd), (ins GPRMem:$rs1, simm12:$imm12),
633 opcodestr, "$rd, ${imm12}(${rs1})">;
648 (ins rty:$rs2, GPRMem:$rs1, simm12:$imm12),
649 opcodestr, "$rs2, ${imm12}(${rs1})">;
661 : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
662 opcodestr, "$rd, $rs1, $imm12">,
682 : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins csr_sysreg:$imm12, GPR:$rs1),
683 opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR, ReadCSR]>;
[all …]
H A DRISCVInstrInfoXqci.td252 bits<12> imm12; // This one is the PC-relative offset
256 let Inst{31} = imm12{11};
257 let Inst{30-25} = imm12{9-4};
261 let Inst{11-8} = imm12{3-0};
262 let Inst{7} = imm12{10};
342 bare_simm13_lsb0:$imm12),
343 "$opcode, $func3, $func5, $rs1, $imm16, $imm12">;
389 def : InstAlias<".insn_qc.eb $opcode, $func3, $func5, $rs1, $imm16, $imm12",
395 bare_simm13_lsb0:$imm12)>;
606 (ins GPRNoX0:$rs1, InTyImm5:$rs2, bare_simm13_lsb0:$imm12),
[all …]
H A DRISCVGISel.td44 def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), simm12:$imm12)),
45 (SLTIU GPR:$rs1, simm12:$imm12)>;
48 def : Pat<(XLenVT (setlt (PtrVT GPR:$rs1), simm12:$imm12)),
49 (SLTI GPR:$rs1, simm12:$imm12)>;
57 def : Pat<(XLenVT (seteq (Ty GPR:$rs1), (Ty simm12Plus1:$imm12))),
58 (SLTIU (ADDI GPR:$rs1, (NegImm simm12Plus1:$imm12)), 1)>;
62 def : Pat<(XLenVT (setne (Ty GPR:$rs1), (Ty simm12Plus1:$imm12))),
63 (SLTU (XLenVT X0), (ADDI GPR:$rs1, (NegImm simm12Plus1:$imm12)))>;
H A DRISCVInstrInfoXCV.td274 (ins GPRMem:$rs1, simm12:$imm12),
275 opcodestr, "$rd, (${rs1}), ${imm12}"> {
295 (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
296 opcodestr, "$rs2, (${rs1}), ${imm12}"> {
335 (ins GPRMem:$rs1, simm12:$imm12), opcodestr, "$rd, ${imm12}(${rs1})">;
591 (ins GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12),
592 "cv.beqimm", "$rs1, $imm5, $imm12">, Sched<[]>;
594 (ins GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12),
595 "cv.bneimm", "$rs1, $imm5, $imm12">, Sched<[]>;
676 : Pat<(StoreOp (XLenVT GPR:$rs2), GPR:$rs1, simm12:$imm12),
[all …]
H A DRISCVInstrInfoF.td199 (ins GPRMem:$rs1, simm12:$imm12),
200 opcodestr, "$rd, ${imm12}(${rs1})">,
207 (ins rty:$rs2, GPRMem:$rs1, simm12:$imm12),
208 opcodestr, "$rs2, ${imm12}(${rs1})">,
H A DRISCVInstrInfoZa.td131 let imm12 = funct12;
H A DRISCVInstrInfoD.td531 def PseudoRV32ZdinxLD : Pseudo<(outs GPRPair:$dst), (ins GPR:$rs1, simm12:$imm12), []>;
535 def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPair:$rs2, GPRNoX0:$rs1, simm12:$imm12), []>;
/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DARMUtils.h310 const uint32_t imm12 = i << 11 | imm3 << 8 | abcdefgh; in ThumbExpandImm_C() local
312 if (bits(imm12, 11, 10) == 0) { in ThumbExpandImm_C()
313 switch (bits(imm12, 9, 8)) { in ThumbExpandImm_C()
335 const uint32_t unrotated_value = 0x80 | bits(imm12, 6, 0); in ThumbExpandImm_C()
336 imm32 = ror(unrotated_value, 32, bits(imm12, 11, 7)); in ThumbExpandImm_C()
355 const uint32_t imm12 = i << 11 | imm3 << 8 | imm8; in ThumbImm12() local
356 return imm12; in ThumbImm12()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloatInstrFormats.td82 bits<12> imm12;
87 let Inst{21-10} = imm12;
209 : FPFmt2RI12<op, (outs rc:$fd), (ins GPR:$rj, simm12_addlike:$imm12),
210 "$fd, $rj, $imm12">;
218 : FPFmt2RI12<op, (outs), (ins rc:$fd, GPR:$rj, simm12_addlike:$imm12),
219 "$fd, $rj, $imm12">;
H A DLoongArchInstrFormats.td169 bits<12> imm12;
174 let Inst{21-10} = imm12;
310 bits<12> imm12;
315 let Inst{21-10} = imm12;
366 bits<12> imm12;
371 let Inst{21-10} = imm12;
H A DLoongArchInstrInfo.td691 : Fmt2RI12<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm12),
692 "$rd, $rj, $imm12">;
733 : Fmt2RI12<op, (outs GPR:$rd), (ins GPR:$rj, simm12_addlike:$imm12),
734 "$rd, $rj, $imm12">;
745 : Fmt2RI12<op, (outs), (ins GPR:$rd, GPR:$rj, simm12_addlike:$imm12),
746 "$rd, $rj, $imm12">;
866 def PRELD : FmtPRELD<(outs), (ins uimm5:$imm5, GPR:$rj, simm12:$imm12),
867 "$imm5, $rj, $imm12">;
890 def CACOP : FmtCACOP<(outs), (ins uimm5:$op, GPR:$rj, simm12:$imm12),
891 "$op, $rj, $imm12">;
[all …]
H A DLoongArchLASXInstrFormats.td391 bits<12> imm12;
396 let Inst{21-10} = imm12;
H A DLoongArchLSXInstrFormats.td418 bits<12> imm12;
423 let Inst{21-10} = imm12;
H A DLoongArchLASXInstrInfo.td194 : Fmt2RI12_XRI<op, (outs LASX256:$xd), (ins GPR:$rj, ImmOpnd:$imm12),
195 "$xd, $rj, $imm12">;
197 : Fmt2RI12_XRI<op, (outs), (ins LASX256:$xd, GPR:$rj, ImmOpnd:$imm12),
198 "$xd, $rj, $imm12">;
H A DLoongArchLSXInstrInfo.td401 : Fmt2RI12_VRI<op, (outs LSX128:$vd), (ins GPR:$rj, ImmOpnd:$imm12),
402 "$vd, $rj, $imm12">;
404 : Fmt2RI12_VRI<op, (outs), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm12),
405 "$vd, $rj, $imm12">;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats.td199 (ins GPR:$rx, ImmType:$imm12), !strconcat(op, "\t$rz, $rx, $imm12"),
200 [(set GPR:$rz, (node GPR:$rx, ImmType:$imm12))]> {
203 bits<12> imm12;
207 let Inst{11 - 0} = imm12;
212 : CSKY32Inst<am, opcode, outs, ins, !strconcat(op, "\t$rz, ($rx, ${imm12})"),
216 bits<12> imm12;
220 let Inst{11 - 0} = imm12;
225 : CSKY32Inst<am, opcode, outs, ins, !strconcat(op, "\t($rx, ${imm12})"),
228 bits<12> imm12;
232 let Inst{11 - 0} = imm12;
[all …]
H A DCSKYInstrInfo.td574 def RSUBI32 : CSKYPseudo<(outs GPR:$rd), (ins GPR:$rx, uimm12:$imm12), "rsubi32 $rd, $rx, $imm12", []>;
694 let InOperandList = (ins GPRPair:$rz, GPR:$rx, uimm12_2:$imm12 ) in
922 (outs GPR:$rd), (ins GPR:$rz, GPR:$rx, uimm12_2:$imm12), "stex32.w", []>;
1069 def PLDR32 :I_PLDR<AddrMode32WD, 0x36, 0b0110, (outs), (ins GPR:$rx, uimm12_2:$imm12), "pldr32", []>;
1070 def PLDW32 :I_PLDR<AddrMode32WD, 0x37, 0b0110, (outs), (ins GPR:$rx, uimm12_2:$imm12), "pldw32", []>;
/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DARM.cpp858 int64_t imm12 = val; in relocate() local
860 if (imm12 < 0) { in relocate()
861 imm12 = -imm12; in relocate()
864 checkUInt(ctx, loc, imm12, 12, rel); in relocate()
866 write16(ctx, loc + 2, (read16(ctx, loc + 2) & 0xf000) | imm12); in relocate()
992 uint32_t imm12 = read32(ctx, buf) & 0xfff; in getImplicitAddend() local
993 return u ? imm12 : -imm12; in getImplicitAddend()
1026 uint64_t imm12 = read16(ctx, buf + 2) & 0x0fff; in getImplicitAddend() local
1027 return u ? imm12 : -imm12; in getImplicitAddend()
H A DRISCV.cpp398 uint32_t imm12 = extractBits(val, 12, 12) << 31; in relocate() local
402 insn |= imm12 | imm10_5 | imm4_1 | imm11; in relocate()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrFormats.td163 bits<12> imm12;
166 let Inst{23-12} = imm12;
H A DXtensaOperands.td54 // imm12 predicate - Immediate in the range [-2048,2047]
56 def imm12 : Immediate<i32, [{ return Imm >= -2048 && Imm <= 2047; }], "Imm12_AsmOperand"> {
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/
H A DEmulateInstructionARM64.cpp620 const uint32_t imm12 = Bits32(opcode, 21, 10); in EmulateADDSUBImm() local
635 imm = imm12; in EmulateADDSUBImm()
638 imm = static_cast<uint64_t>(imm12) << 12; in EmulateADDSUBImm()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrInfo.td1140 // addrmode_imm12 := reg +/- imm12
2055 let Inst{11-0} = addr{11-0}; // imm12
2086 let Inst{11-0} = addr{11-0}; // imm12
2118 let Inst{11-0} = addr{11-0}; // imm12
2147 let Inst{11-0} = addr{11-0}; // imm12
2330 let Inst{11-0} = addr{11-0}; // imm12
2873 let Inst{11-0} = addr{11-0}; // imm12
2944 // {11-0} imm12/Rm
2962 // {11-0} imm12/Rm
3054 // {11-0} imm12/Rm
[all …]

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