| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchLSXInstrFormats.td | 74 bits<1> imm1;
79 let Inst{10} = imm1;
88 bits<1> imm1;
93 let Inst{10} = imm1;
102 bits<1> imm1;
107 let Inst{10} = imm1;
306 bits<1> imm1;
312 let Inst{18} = imm1;
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| H A D | LoongArchLASXInstrFormats.td | 74 bits<1> imm1;
79 let Inst{10} = imm1;
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| H A D | LoongArchLSXInstrInfo.td | 221 : Fmt2RI1_VVI<op, (outs LSX128:$vd), (ins LSX128:$vj, ImmOpnd:$imm1),
222 "$vd, $vj, $imm1">;
225 : Fmt2RI1_RVI<op, (outs GPR:$rd), (ins LSX128:$vj, ImmOpnd:$imm1),
226 "$rd, $vj, $imm1">;
267 (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm8, IdxOpnd:$imm1),
268 "$vd, $rj, $imm8, $imm1">;
301 : Fmt2RI1_VRI<op, (outs LSX128:$dst), (ins LSX128:$vd, GPR:$rj, ImmOpnd:$imm1),
302 "$vd, $rj, $imm1">;
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| H A D | LoongArchInstrInfo.td | 528 // Check if (add r, imm) can be optimized to (ADDI (ADDI r, imm0), imm1),
529 // in which imm = imm0 + imm1, and both imm0 & imm1 are simm12.
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| H A D | LoongArchLASXInstrInfo.td | 63 : Fmt2RI1_XXI<op, (outs LASX256:$xd), (ins LASX256:$xj, ImmOpnd:$imm1),
64 "$xd, $xj, $imm1">;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaInstrInfo.td | 140 def EXTUI : RRR_Inst<0x00, 0x04, 0x00, (outs AR:$r), (ins AR:$t, uimm5:$imm1, imm1_16:$imm2),
141 "extui\t$r, $t, $imm1, $imm2", []> {
142 bits<5> imm1;
145 let s = imm1{3-0};
146 let Inst{16} = imm1{4};
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/ |
| H A D | Combine.td | 1030 (G_CONSTANT $lsb, $imm1),
1613 (match (G_VSCALE $left, $imm1),
1622 (G_CONSTANT $x, $imm1),
1630 (G_CONSTANT $x, $imm1),
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.td | 429 // Check if (add r, imm) can be optimized to (ADDI (ADDI r, imm0), imm1),
430 // in which imm = imm0 + imm1 and both imm0 and imm1 are simm12. We make imm0
431 // as large as possible and imm1 as small as possible so that we might be able
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 232 unsigned Op0, uint64_t imm1, uint64_t imm2, in fastEmitInst_riir() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrP10.td | 439 // PO T XO TX imm1 ].
464 // PO T XO IX TX imm1 ].
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | SMEInstrFormats.td | 238 // MSR SVCRSM, #<imm1>
239 // MSR SVCRZA, #<imm1>
240 // MSR SVCRSMZA, #<imm1>
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| H A D | AArch64InstrFormats.td | 1220 // {0} - imm1: #8 or #16
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrFormats.td | 3361 ImmOpWithPattern imm1, ImmOpWithPattern imm2>
3362 : InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2),
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.td | 4883 // SETPAN #imm1
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| H A D | ARMInstrThumb2.td | 4787 // SETPAN #imm1
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXIntrinsics.td | 1593 def imm1 : NVPTXInst<(outs regclass:$dst),
|