1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 #ifndef _ICP_QAT_HW_H_ 4 #define _ICP_QAT_HW_H_ 5 6 enum icp_qat_hw_ae_id { 7 ICP_QAT_HW_AE_0 = 0, 8 ICP_QAT_HW_AE_1 = 1, 9 ICP_QAT_HW_AE_2 = 2, 10 ICP_QAT_HW_AE_3 = 3, 11 ICP_QAT_HW_AE_4 = 4, 12 ICP_QAT_HW_AE_5 = 5, 13 ICP_QAT_HW_AE_6 = 6, 14 ICP_QAT_HW_AE_7 = 7, 15 ICP_QAT_HW_AE_8 = 8, 16 ICP_QAT_HW_AE_9 = 9, 17 ICP_QAT_HW_AE_10 = 10, 18 ICP_QAT_HW_AE_11 = 11, 19 ICP_QAT_HW_AE_DELIMITER = 12 20 }; 21 22 enum icp_qat_hw_qat_id { 23 ICP_QAT_HW_QAT_0 = 0, 24 ICP_QAT_HW_QAT_1 = 1, 25 ICP_QAT_HW_QAT_2 = 2, 26 ICP_QAT_HW_QAT_3 = 3, 27 ICP_QAT_HW_QAT_4 = 4, 28 ICP_QAT_HW_QAT_5 = 5, 29 ICP_QAT_HW_QAT_DELIMITER = 6 30 }; 31 32 enum icp_qat_hw_auth_algo { 33 ICP_QAT_HW_AUTH_ALGO_NULL = 0, 34 ICP_QAT_HW_AUTH_ALGO_SHA1 = 1, 35 ICP_QAT_HW_AUTH_ALGO_MD5 = 2, 36 ICP_QAT_HW_AUTH_ALGO_SHA224 = 3, 37 ICP_QAT_HW_AUTH_ALGO_SHA256 = 4, 38 ICP_QAT_HW_AUTH_ALGO_SHA384 = 5, 39 ICP_QAT_HW_AUTH_ALGO_SHA512 = 6, 40 ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC = 7, 41 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8, 42 ICP_QAT_HW_AUTH_ALGO_AES_F9 = 9, 43 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 = 10, 44 ICP_QAT_HW_AUTH_ALGO_GALOIS_64 = 11, 45 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12, 46 ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13, 47 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14, 48 ICP_QAT_HW_AUTH_RESERVED_1 = 15, 49 ICP_QAT_HW_AUTH_RESERVED_2 = 16, 50 ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17, 51 ICP_QAT_HW_AUTH_RESERVED_3 = 18, 52 ICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19, 53 ICP_QAT_HW_AUTH_ALGO_DELIMITER = 20 54 }; 55 56 enum icp_qat_hw_auth_mode { 57 ICP_QAT_HW_AUTH_MODE0 = 0, 58 ICP_QAT_HW_AUTH_MODE1 = 1, 59 ICP_QAT_HW_AUTH_MODE2 = 2, 60 ICP_QAT_HW_AUTH_MODE_DELIMITER = 3 61 }; 62 63 struct icp_qat_hw_auth_config { 64 uint32_t config; 65 uint32_t reserved; 66 }; 67 enum icp_qat_slice_mask { 68 ICP_ACCEL_MASK_CIPHER_SLICE = 0x01, 69 ICP_ACCEL_MASK_AUTH_SLICE = 0x02, 70 ICP_ACCEL_MASK_PKE_SLICE = 0x04, 71 ICP_ACCEL_MASK_COMPRESS_SLICE = 0x08, 72 ICP_ACCEL_MASK_DEPRECATED = 0x10, 73 ICP_ACCEL_MASK_EIA3_SLICE = 0x20, 74 ICP_ACCEL_MASK_SHA3_SLICE = 0x40, 75 ICP_ACCEL_MASK_CRYPTO0_SLICE = 0x80, 76 ICP_ACCEL_MASK_CRYPTO1_SLICE = 0x100, 77 ICP_ACCEL_MASK_CRYPTO2_SLICE = 0x200, 78 ICP_ACCEL_MASK_SM3_SLICE = 0x400, 79 ICP_ACCEL_MASK_SM4_SLICE = 0x800 80 }; 81 82 enum icp_qat_capabilities_mask { 83 ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = BIT(0), 84 ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = BIT(1), 85 ICP_ACCEL_CAPABILITIES_CIPHER = BIT(2), 86 ICP_ACCEL_CAPABILITIES_AUTHENTICATION = BIT(3), 87 ICP_ACCEL_CAPABILITIES_RESERVED_1 = BIT(4), 88 ICP_ACCEL_CAPABILITIES_COMPRESSION = BIT(5), 89 ICP_ACCEL_CAPABILITIES_DEPRECATED = BIT(6), 90 ICP_ACCEL_CAPABILITIES_RAND = BIT(7), 91 ICP_ACCEL_CAPABILITIES_ZUC = BIT(8), 92 ICP_ACCEL_CAPABILITIES_SHA3 = BIT(9), 93 ICP_ACCEL_CAPABILITIES_KPT = BIT(10), 94 ICP_ACCEL_CAPABILITIES_RL = BIT(11), 95 ICP_ACCEL_CAPABILITIES_HKDF = BIT(12), 96 ICP_ACCEL_CAPABILITIES_ECEDMONT = BIT(13), 97 ICP_ACCEL_CAPABILITIES_EXT_ALGCHAIN = BIT(14), 98 ICP_ACCEL_CAPABILITIES_SHA3_EXT = BIT(15), 99 ICP_ACCEL_CAPABILITIES_AESGCM_SPC = BIT(16), 100 ICP_ACCEL_CAPABILITIES_CHACHA_POLY = BIT(17), 101 ICP_ACCEL_CAPABILITIES_SM2 = BIT(18), 102 ICP_ACCEL_CAPABILITIES_SM3 = BIT(19), 103 ICP_ACCEL_CAPABILITIES_SM4 = BIT(20), 104 ICP_ACCEL_CAPABILITIES_INLINE = BIT(21), 105 ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY = BIT(22), 106 ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64 = BIT(23), 107 ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION = BIT(24), 108 ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION = BIT(25), 109 ICP_ACCEL_CAPABILITIES_AES_V2 = BIT(26), 110 ICP_ACCEL_CAPABILITIES_KPT2 = BIT(27), 111 }; 112 113 enum icp_qat_extended_dc_capabilities_mask { 114 ICP_ACCEL_CAPABILITIES_ADVANCED_COMPRESSION = 0x101 115 }; 116 117 #define QAT_AUTH_MODE_BITPOS 4 118 #define QAT_AUTH_MODE_MASK 0xF 119 #define QAT_AUTH_ALGO_BITPOS 0 120 #define QAT_AUTH_ALGO_MASK 0xF 121 #define QAT_AUTH_CMP_BITPOS 8 122 #define QAT_AUTH_HIGH_BIT 4 123 #define QAT_AUTH_CMP_MASK 0x7F 124 #define QAT_AUTH_SHA3_PADDING_BITPOS 16 125 #define QAT_AUTH_SHA3_PADDING_MASK 0x1 126 #define QAT_AUTH_ALGO_SHA3_BITPOS 22 127 #define QAT_AUTH_ALGO_SHA3_MASK 0x3 128 #define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \ 129 (((mode & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \ 130 ((algo & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \ 131 (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) \ 132 << QAT_AUTH_ALGO_SHA3_BITPOS) | \ 133 (((((algo == ICP_QAT_HW_AUTH_ALGO_SHA3_256) || \ 134 (algo == ICP_QAT_HW_AUTH_ALGO_SHA3_512)) ? \ 135 1 : \ 136 0) & \ 137 QAT_AUTH_SHA3_PADDING_MASK) \ 138 << QAT_AUTH_SHA3_PADDING_BITPOS) | \ 139 ((cmp_len & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS)) 140 141 struct icp_qat_hw_auth_counter { 142 __be32 counter; 143 uint32_t reserved; 144 }; 145 146 #define QAT_AUTH_COUNT_MASK 0xFFFFFFFF 147 #define QAT_AUTH_COUNT_BITPOS 0 148 #define ICP_QAT_HW_AUTH_COUNT_BUILD(val) \ 149 (((val)&QAT_AUTH_COUNT_MASK) << QAT_AUTH_COUNT_BITPOS) 150 151 struct icp_qat_hw_auth_setup { 152 struct icp_qat_hw_auth_config auth_config; 153 struct icp_qat_hw_auth_counter auth_counter; 154 }; 155 156 #define QAT_HW_DEFAULT_ALIGNMENT 8 157 #define QAT_HW_ROUND_UP(val, n) (((val) + ((n)-1)) & (~(n - 1))) 158 #define ICP_QAT_HW_NULL_STATE1_SZ 32 159 #define ICP_QAT_HW_MD5_STATE1_SZ 16 160 #define ICP_QAT_HW_SHA1_STATE1_SZ 20 161 #define ICP_QAT_HW_SHA224_STATE1_SZ 32 162 #define ICP_QAT_HW_SHA256_STATE1_SZ 32 163 #define ICP_QAT_HW_SHA3_256_STATE1_SZ 32 164 #define ICP_QAT_HW_SHA384_STATE1_SZ 64 165 #define ICP_QAT_HW_SHA512_STATE1_SZ 64 166 #define ICP_QAT_HW_SHA3_512_STATE1_SZ 64 167 #define ICP_QAT_HW_SHA3_224_STATE1_SZ 28 168 #define ICP_QAT_HW_SHA3_384_STATE1_SZ 48 169 #define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16 170 #define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16 171 #define ICP_QAT_HW_AES_F9_STATE1_SZ 32 172 #define ICP_QAT_HW_KASUMI_F9_STATE1_SZ 16 173 #define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16 174 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8 175 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8 176 #define ICP_QAT_HW_NULL_STATE2_SZ 32 177 #define ICP_QAT_HW_MD5_STATE2_SZ 16 178 #define ICP_QAT_HW_SHA1_STATE2_SZ 20 179 #define ICP_QAT_HW_SHA224_STATE2_SZ 32 180 #define ICP_QAT_HW_SHA256_STATE2_SZ 32 181 #define ICP_QAT_HW_SHA3_256_STATE2_SZ 0 182 #define ICP_QAT_HW_SHA384_STATE2_SZ 64 183 #define ICP_QAT_HW_SHA512_STATE2_SZ 64 184 #define ICP_QAT_HW_SHA3_512_STATE2_SZ 0 185 #define ICP_QAT_HW_SHA3_224_STATE2_SZ 0 186 #define ICP_QAT_HW_SHA3_384_STATE2_SZ 0 187 #define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16 188 #define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16 189 #define ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ 16 190 #define ICP_QAT_HW_F9_IK_SZ 16 191 #define ICP_QAT_HW_F9_FK_SZ 16 192 #define ICP_QAT_HW_KASUMI_F9_STATE2_SZ \ 193 (ICP_QAT_HW_F9_IK_SZ + ICP_QAT_HW_F9_FK_SZ) 194 #define ICP_QAT_HW_AES_F9_STATE2_SZ ICP_QAT_HW_KASUMI_F9_STATE2_SZ 195 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ 24 196 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ 32 197 #define ICP_QAT_HW_GALOIS_H_SZ 16 198 #define ICP_QAT_HW_GALOIS_LEN_A_SZ 8 199 #define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16 200 201 struct icp_qat_hw_auth_sha512 { 202 struct icp_qat_hw_auth_setup inner_setup; 203 uint8_t state1[ICP_QAT_HW_SHA512_STATE1_SZ]; 204 struct icp_qat_hw_auth_setup outer_setup; 205 uint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ]; 206 }; 207 208 struct icp_qat_hw_auth_algo_blk { 209 struct icp_qat_hw_auth_sha512 sha; 210 }; 211 212 #define ICP_QAT_HW_GALOIS_LEN_A_BITPOS 0 213 #define ICP_QAT_HW_GALOIS_LEN_A_MASK 0xFFFFFFFF 214 215 enum icp_qat_hw_cipher_algo { 216 ICP_QAT_HW_CIPHER_ALGO_NULL = 0, 217 ICP_QAT_HW_CIPHER_ALGO_DES = 1, 218 ICP_QAT_HW_CIPHER_ALGO_3DES = 2, 219 ICP_QAT_HW_CIPHER_ALGO_AES128 = 3, 220 ICP_QAT_HW_CIPHER_ALGO_AES192 = 4, 221 ICP_QAT_HW_CIPHER_ALGO_AES256 = 5, 222 ICP_QAT_HW_CIPHER_ALGO_ARC4 = 6, 223 ICP_QAT_HW_CIPHER_ALGO_KASUMI = 7, 224 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8, 225 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9, 226 ICP_QAT_HW_CIPHER_ALGO_SM4 = 10, 227 ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305 = 11, 228 ICP_QAT_HW_CIPHER_DELIMITER = 12 229 }; 230 231 enum icp_qat_hw_cipher_mode { 232 ICP_QAT_HW_CIPHER_ECB_MODE = 0, 233 ICP_QAT_HW_CIPHER_CBC_MODE = 1, 234 ICP_QAT_HW_CIPHER_CTR_MODE = 2, 235 ICP_QAT_HW_CIPHER_F8_MODE = 3, 236 ICP_QAT_HW_CIPHER_AEAD_MODE = 4, 237 ICP_QAT_HW_CIPHER_RESERVED_MODE = 5, 238 ICP_QAT_HW_CIPHER_XTS_MODE = 6, 239 ICP_QAT_HW_CIPHER_MODE_DELIMITER = 7 240 }; 241 242 struct icp_qat_hw_cipher_config { 243 uint32_t val; 244 uint32_t reserved; 245 }; 246 247 enum icp_qat_hw_cipher_dir { 248 ICP_QAT_HW_CIPHER_ENCRYPT = 0, 249 ICP_QAT_HW_CIPHER_DECRYPT = 1, 250 }; 251 252 enum icp_qat_hw_cipher_convert { 253 ICP_QAT_HW_CIPHER_NO_CONVERT = 0, 254 ICP_QAT_HW_CIPHER_KEY_CONVERT = 1, 255 }; 256 257 #define QAT_CIPHER_MODE_BITPOS 4 258 #define QAT_CIPHER_MODE_MASK 0xF 259 #define QAT_CIPHER_ALGO_BITPOS 0 260 #define QAT_CIPHER_ALGO_MASK 0xF 261 #define QAT_CIPHER_CONVERT_BITPOS 9 262 #define QAT_CIPHER_CONVERT_MASK 0x1 263 #define QAT_CIPHER_DIR_BITPOS 8 264 #define QAT_CIPHER_DIR_MASK 0x1 265 #define QAT_CIPHER_AEAD_HASH_CMP_LEN_MASK 0x1F 266 #define QAT_CIPHER_AEAD_HASH_CMP_LEN_BITPOS 10 267 #define QAT_CIPHER_AEAD_AAD_SIZE_LOWER_MASK 0xFF 268 #define QAT_CIPHER_AEAD_AAD_SIZE_UPPER_MASK 0x3F 269 #define QAT_CIPHER_AEAD_AAD_UPPER_SHIFT 8 270 #define QAT_CIPHER_AEAD_AAD_LOWER_SHIFT 24 271 #define QAT_CIPHER_AEAD_AAD_SIZE_BITPOS 16 272 #define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2 273 #define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2 274 #define ICP_QAT_HW_CIPHER_CONFIG_BUILD(mode, algo, convert, dir) \ 275 (((mode & QAT_CIPHER_MODE_MASK) << QAT_CIPHER_MODE_BITPOS) | \ 276 ((algo & QAT_CIPHER_ALGO_MASK) << QAT_CIPHER_ALGO_BITPOS) | \ 277 ((convert & QAT_CIPHER_CONVERT_MASK) << QAT_CIPHER_CONVERT_BITPOS) | \ 278 ((dir & QAT_CIPHER_DIR_MASK) << QAT_CIPHER_DIR_BITPOS)) 279 #define ICP_QAT_HW_DES_BLK_SZ 8 280 #define ICP_QAT_HW_3DES_BLK_SZ 8 281 #define ICP_QAT_HW_NULL_BLK_SZ 8 282 #define ICP_QAT_HW_AES_BLK_SZ 16 283 #define ICP_QAT_HW_KASUMI_BLK_SZ 8 284 #define ICP_QAT_HW_SNOW_3G_BLK_SZ 8 285 #define ICP_QAT_HW_ZUC_3G_BLK_SZ 8 286 #define ICP_QAT_HW_NULL_KEY_SZ 256 287 #define ICP_QAT_HW_DES_KEY_SZ 8 288 #define ICP_QAT_HW_3DES_KEY_SZ 24 289 #define ICP_QAT_HW_AES_128_KEY_SZ 16 290 #define ICP_QAT_HW_AES_192_KEY_SZ 24 291 #define ICP_QAT_HW_AES_256_KEY_SZ 32 292 #define ICP_QAT_HW_AES_128_F8_KEY_SZ \ 293 (ICP_QAT_HW_AES_128_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 294 #define ICP_QAT_HW_AES_192_F8_KEY_SZ \ 295 (ICP_QAT_HW_AES_192_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 296 #define ICP_QAT_HW_AES_256_F8_KEY_SZ \ 297 (ICP_QAT_HW_AES_256_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 298 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ \ 299 (ICP_QAT_HW_AES_128_KEY_SZ * QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 300 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ \ 301 (ICP_QAT_HW_AES_256_KEY_SZ * QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 302 #define ICP_QAT_HW_KASUMI_KEY_SZ 16 303 #define ICP_QAT_HW_KASUMI_F8_KEY_SZ \ 304 (ICP_QAT_HW_KASUMI_KEY_SZ * QAT_CIPHER_MODE_F8_KEY_SZ_MULT) 305 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ \ 306 (ICP_QAT_HW_AES_128_KEY_SZ * QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 307 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ \ 308 (ICP_QAT_HW_AES_256_KEY_SZ * QAT_CIPHER_MODE_XTS_KEY_SZ_MULT) 309 #define ICP_QAT_HW_ARC4_KEY_SZ 256 310 #define ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ 16 311 #define ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ 16 312 #define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ 16 313 #define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ 16 314 #define ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR 2 315 #define INIT_SHRAM_CONSTANTS_TABLE_SZ 1024 316 317 struct icp_qat_hw_cipher_aes256_f8 { 318 struct icp_qat_hw_cipher_config cipher_config; 319 uint8_t key[ICP_QAT_HW_AES_256_F8_KEY_SZ]; 320 }; 321 322 struct icp_qat_hw_cipher_algo_blk { 323 struct icp_qat_hw_cipher_aes256_f8 aes; 324 } __aligned(64); 325 #endif 326