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/freebsd/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/aggs/
H A Dtst.signedkeyspos.d66 @i16["mouse", (short)-2] = sum(-2);
67 @i16["dog", (short)-2] = sum(-22);
68 @i16["cat", (short)-2] = sum(-222);
69 @i16["mouse", (short)-1] = sum(-1);
70 @i16["dog", (short)-1] = sum(-11);
71 @i16["cat", (short)-1] = sum(-111);
72 @i16["mouse", (short)0] = sum(0);
73 @i16["dog", (short)0] = sum(10);
74 @i16["cat", (short)0] = sum(100);
75 @i16["mouse", (short)1] = sum(1);
[all …]
H A Dtst.signedkeys.d101 @i16[(short)-2] = sum(-2);
102 @i16[(short)-1] = sum(-1);
103 @i16[(short)0] = sum(0);
104 @i16[(short)1] = sum(1);
105 @i16[(short)2] = sum(2);
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kExpandPseudo.cpp85 return TII->ExpandMOVI(MIB, MVT::i16); in INITIALIZE_PASS()
90 return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8); in INITIALIZE_PASS()
94 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i16); in INITIALIZE_PASS()
97 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i16, MVT::i8); in INITIALIZE_PASS()
101 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i16); in INITIALIZE_PASS()
104 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i16, MVT::i8); in INITIALIZE_PASS()
108 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i32, MVT::i16); in INITIALIZE_PASS()
111 return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dj), MVT::i16, in INITIALIZE_PASS()
118 MVT::i16); in INITIALIZE_PASS()
121 return TII->ExpandMOVSZX_RM(MIB, false, TII->get(M68k::MOV8dj), MVT::i16, in INITIALIZE_PASS()
[all …]
H A DM68kInstrArithmetic.td561 def : Pat<(sext_inreg i16:$src, i8), (EXT16 $src)>;
562 def : Pat<(sext_inreg i32:$src, i16), (EXT32 $src)>;
642 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
666 // RR i16
667 def : Pat<(sdiv i16:$dst, i16:$opd),
672 def : Pat<(udiv i16:$dst, i16:$opd),
677 def : Pat<(srem i16:$dst, i16:$opd),
682 def : Pat<(urem i16:$dst, i16:$opd),
708 // RI i16
709 def : Pat<(sdiv i16:$dst, Mxi16immSExt16:$opd),
[all …]
H A DM68kCallingConv.td30 CCIfType<[i16], CCAssignToReg<[WD0, WD1]>>,
42 CCIfType<[i16], CCAssignToReg<[WD0, WD1, WA0, WA1]>>,
68 /// Promote i1/i8/i16 arguments to i32.
69 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
83 /// Promote i1/i8/i16 arguments to i32.
84 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
H A DM68kRegisterInfo.td105 def DR16 : MxRegClass<[i16], 16, (sequence "WD%u", 0, 7)>;
111 def AR16 : MxRegClass<[i16], 16, (add (sequence "WA%u", 0, 6), WSP)>;
121 def XR16 : MxRegClass<[i16], 16, (add DR16, AR16)>;
140 def SRC : MxRegClass<[i16], 16, (add SR)>;
157 def DR16_TC : MxRegClass<[i16], 16, (add D0, D1)>;
162 def AR16_TC : MxRegClass<[i16], 16, (add A0, A1)>;
167 def XR16_TC : MxRegClass<[i16], 16, (add DR16_TC, AR16_TC)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.td19 def SDT_AVRCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
20 def SDT_AVRCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
116 return CurDAG->getTargetConstant(-N->getAPIntValue(), SDLoc(N), MVT::i16);
214 def rcalltarget_13 : Operand<i16> {
226 def imm16 : Operand<i16> { let EncoderMethod = "encodeImm<AVR::fixup_16, 2>"; }
229 def imm7tiny : Operand<i16> {
234 def imm_arith6 : Operand<i16> {
375 [(set i16:$rd, (add i16:$src, i16:$rr))]>;
394 [(set i16:$rd, (adde i16:$src, i16:$rr))]>;
400 [(set i16:$rd, (add i16:$src, uimm6:$k))]>,
[all …]
H A DAVRISelLowering.cpp40 addRegisterClass(MVT::i16, &AVR::DREGSRegClass); in AVRTargetLowering()
51 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); in AVRTargetLowering()
52 setOperationAction(ISD::BlockAddress, MVT::i16, Custom); in AVRTargetLowering()
57 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand); in AVRTargetLowering()
68 setTruncStoreAction(MVT::i16, MVT::i8, Expand); in AVRTargetLowering()
87 setOperationAction(ISD::SRA, MVT::i16, Custom); in AVRTargetLowering()
88 setOperationAction(ISD::SHL, MVT::i16, Custom); in AVRTargetLowering()
89 setOperationAction(ISD::SRL, MVT::i16, Custom); in AVRTargetLowering()
93 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand); in AVRTargetLowering()
94 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand); in AVRTargetLowering()
[all …]
H A DAVRISelDAGToDAG.cpp116 Disp = CurDAG->getTargetConstant(RHSC, dl, MVT::i16); in SelectAddr()
129 bool OkI16 = VT == MVT::i16 && RHSC <= 62; in SelectAddr()
168 case MVT::i16: { in selectIndexedLoad()
327 TFI, CurDAG->getTargetConstant(0, SDLoc(N), MVT::i16)); in select()
353 SDValue Offset = CurDAG->getTargetConstant(CST, DL, MVT::i16); in select()
355 unsigned Opc = (VT == MVT::i16) ? AVR::STDWSPQRr : AVR::STDSPQRr; in select()
393 Ptr = CurDAG->getCopyFromReg(Chain, DL, AVR::R31R30, MVT::i16, in select()
401 CurDAG->getMachineNode(LPMOpc, DL, VT, MVT::i16, MVT::Other, Ptr); in select()
407 ResNode = CurDAG->getMachineNode(LPMOpc, DL, VT, MVT::i16, MVT::Other, in select()
426 case MVT::i16: in select()
[all …]
H A DAVRRegisterInfo.td97 // Pseudo registers for unaligned i16
142 def DREGS : RegisterClass<"AVR", [i16], 8,
156 : RegisterClass<"AVR", [i16], 8,
160 def DREGSLD8lo : RegisterClass<"AVR", [i16], 8,
167 def DREGSMOVW : RegisterClass<"AVR", [i16], 8,
177 def DLDREGS : RegisterClass<"AVR", [i16], 8,
186 def IWREGS : RegisterClass<"AVR", [i16], 8,
196 def PTRREGS : RegisterClass<"AVR", [i16], 8,
204 def PTRDISPREGS : RegisterClass<"AVR", [i16], 8, (add R31R30, R29R28), ptr>;
208 def ZREG : RegisterClass<"AVR", [i16], 8, (add R31R30)>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVGISel.td103 // Load and store patterns for i16, needed because Zfh makes s16 load/store
105 def : LdPat<load, LH, i16>;
106 def : StPat<store, SH, GPR, i16>;
108 def : LdPat<extloadi8, LBU, i16>; // Prefer unsigned due to no c.lb in Zcb.
109 def : StPat<truncstorei8, SB, GPR, i16>;
112 def : LdPat<atomic_load_aext_8, LB, i16>;
113 def : LdPat<atomic_load_nonext_16, LH, i16>;
115 def : StPat<atomic_store_8, SB, GPR, i16>;
116 def : StPat<atomic_store_16, SH, GPR, i16>;
154 def : Pat<(XLenVT (zext (i16 GPR:$src))),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallingConv.td25 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
29 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
33 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>>
38 CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
40 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
49 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
54 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
60 CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
61 CCIfType<[i32, i16, v2i16] , CCAssignToReg<
135 CCIfType<[i8, i16], CCIfExtend<CCPromoteToType<i32>>>,
[all …]
H A DSIInstructions.td1360 def : VOPSelectPat <i16>;
1364 def : VOPSelectPat_t16 <i16>;
1380 (i16 (add (i16 (trunc (i32 (DivergentUnaryFrag<ctpop> i32:$popcnt)))), i16:$val)),
2039 (V_AND_B16_t16_e64 (i32 0), (i16 0x7fff), (i32 0), VGPR_16:$src)
2044 (V_XOR_B16_t16_e64 (i32 0), (i16 0x8000), (i32 0), VGPR_16:$src)
2049 (V_OR_B16_t16_e64 (i32 0), (i16 0x8000), (i32 0), VGPR_16:$src) // Set sign bit
2200 (VGPRImm<(i16 imm)>:$imm),
2219 (VGPRImm<(i16 imm)>:$imm),
2333 …(REG_SEQUENCE VGPR_32, (i16 (EXTRACT_SUBREG $src, hi16)), lo16, (V_MOV_B16_t16_e64 0, (i16 0x0000)…
2525 (i16 (EXTRACT_SUBREG VGPR_32:$src1, lo16)),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp259 AM.Base.Reg = CurDAG->getRegister(MSP430::SR, MVT::i16); in SelectAddr()
269 MVT::i16, AM.Disp, in SelectAddr()
272 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16, AM.Alignment, AM.Disp, in SelectAddr()
275 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/); in SelectAddr()
277 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/); in SelectAddr()
282 Disp = CurDAG->getSignedTargetConstant(AM.Disp, SDLoc(N), MVT::i16); in SelectAddr()
317 case MVT::i16: in isValidIndexedLoad()
341 case MVT::i16: in tryIndexedLoad()
349 CurDAG->getMachineNode(Opcode, SDLoc(N), VT, MVT::i16, MVT::Other, in tryIndexedLoad()
364 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8); in tryIndexedBinOp()
[all …]
H A DMSP430ISelLowering.cpp49 addRegisterClass(MVT::i16, &MSP430::GR16RegClass); in MSP430TargetLowering()
61 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in MSP430TargetLowering()
68 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); in MSP430TargetLowering()
72 setTruncStoreAction(MVT::i16, MVT::i8, Expand); in MSP430TargetLowering()
77 setOperationAction(ISD::SRA, MVT::i16, Custom); in MSP430TargetLowering()
78 setOperationAction(ISD::SHL, MVT::i16, Custom); in MSP430TargetLowering()
79 setOperationAction(ISD::SRL, MVT::i16, Custom); in MSP430TargetLowering()
82 setOperationAction(ISD::ROTL, MVT::i16, Expand); in MSP430TargetLowering()
83 setOperationAction(ISD::ROTR, MVT::i16, Expand); in MSP430TargetLowering()
84 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); in MSP430TargetLowering()
[all …]
H A DMSP430CallingConv.td18 // i16 are returned in registers R12, R13, R14, R15
19 CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
29 // Promote i8 arguments to i16.
30 CCIfType<[i8], CCPromoteToType<i16>>,
34 CCIfType<[i16], CCAssignToStack<2, 2>>
H A DMSP430InstrInfo.td19 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
25 def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>,
26 SDTCisVT<1, i16>]>;
27 def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
78 def memsrc : Operand<i16> {
86 def memdst : Operand<i16> {
99 def indreg : Operand<i16> {
111 def postreg : Operand<i16> {
143 def cg16imm : Operand<i16>,
144 ImmLeaf<i16, [{return Imm == 0 || Imm == 1 || Imm == 2 ||
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA55.td389 def : InstRW<[CortexA55WriteAluVd_3], (instregex "[SU]ABDv(2i32|4i16|8i8)")>;
390 def : InstRW<[CortexA55WriteAluVq_3], (instregex "[SU]ABDv(16i8|4i32|8i16)")>;
396 def : InstRW<[CortexA55WriteAluVd_2], (instregex "(ADD|SUB|NEG)v(1i64|2i32|4i16|8i8)",
397 "[SU]R?HADDv(2i32|4i16|8i8)", "[SU]HSUBv(2i32|4i16|8i8)")>;
398 def : InstRW<[CortexA55WriteAluVq_2], (instregex "(ADD|SUB|NEG)v(2i64|4i32|8i16|16i8)",
399 "[SU]R?HADDv(8i16|4i32|16i8)", "[SU]HSUBv(8i16|4i32|16i8)")>;
401 def : InstRW<[CortexA55WriteAluVd_3], (instregex "ABSv(1i64|2i32|4i16|8i8)$",
403 "([SU]QADD|[SU]QSUB|SQNEG|SUQADD|USQADD)v(1i16|
[all...]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.td78 def i16 : VTInt<16, 6>; // 16-bit integer value
125 def v1i16 : VTVec<1, i16, 47>; // 1 x i16 vector value
126 def v2i16 : VTVec<2, i16, 48>; // 2 x i16 vector value
127 def v3i16 : VTVec<3, i16, 49>; // 3 x i16 vector value
128 def v4i16 : VTVec<4, i16, 50>; // 4 x i16 vector value
129 def v8i16 : VTVec<8, i16, 51>; // 8 x i16 vector value
130 def v16i16 : VTVec<16, i16, 52>; // 16 x i16 vector value
131 def v32i16 : VTVec<32, i16, 53>; // 32 x i16 vector value
132 def v64i16 : VTVec<64, i16, 54>; // 64 x i16 vector value
133 def v128i16 : VTVec<128, i16, 55>; // 128 x i16 vector value
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiCallingConv.td19 // Promote i8/i16 args to i32
20 CCIfType<[i8, i16], CCPromoteToType<i32>>,
32 // Promote i8/i16 args to i32
33 CCIfType<[ i8, i16 ], CCPromoteToType<i32>>,
/freebsd/sys/dev/bhnd/nvram/
H A Dnvram_map772 i16 pa0b0 {
777 i16 pa0b1 {
782 i16 pa0b2 {
797 i16 pa1b0 {
802 i16 pa1b1 {
807 i16 pa1b2 {
812 i16 pa1hib0 {
817 i16 pa1hib1 {
822 i16 pa1hib2 {
837 i16 pa1lob0 {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td192 def I16RT : RegTyInfo<i16, B16, "b16", i16imm, imm>;
815 defm ABS_16 : ABS<i16, B16, ".s16">;
868 def : Pat<(i32 (mul_wide_signed i16:$a, i16:$b)), (MULWIDES32 $a, $b)>;
869 def : Pat<(i32 (mul_wide_signed i16:$a, imm:$b)), (MULWIDES32Imm $a, imm:$b)>;
870 def : Pat<(i32 (mul_wide_unsigned i16:$a, i16:$b)), (MULWIDEU32 $a, $b)>;
871 def : Pat<(i32 (mul_wide_unsigned i16:$a, imm:$b)), (MULWIDEU32Imm $a, imm:$b)>;
921 return CurDAG->getTargetConstant(temp.shl(v), SDLoc(N), MVT::i16);
931 def : Pat<(shl (sext i16:$a), (i16 IntConst_0_14:$b)),
933 def : Pat<(shl (zext i16:$a), (i16 IntConst_0_14:$b)),
947 def : Pat<(mul (sext i16:$a), (sext i16:$b)),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECallingConv.td31 // Promote i1/i8/i16/i32 arguments to i64.
32 CCIfType<[i1, i8, i16, i32], CCPromoteToType<i64>>,
62 // Promote i1/i8/i16/i32 arguments to i64.
63 CCIfType<[i1, i8, i16, i32], CCPromoteToType<i64>>,
79 // Promote i1/i8/i16/i32 return values to i64.
80 CCIfType<[i1, i8, i16, i32], CCPromoteToType<i64>>,
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYCallingConv.td44 CCIfType<[i8, i16], CCPromoteToType<i32>>,
56 CCIfType<[i8, i16], CCPromoteToType<i32>>,
66 CCIfType<[i8, i16], CCPromoteToType<i32>>,
78 CCIfType<[i8, i16], CCPromoteToType<i32>>,
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallingConv.td119 // Promote i1/i8/i16/v1i1 arguments to i32.
120 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
192 // Promote v16i1 arguments to i16.
193 CCIfType<[v16i1], CCPromoteToType<i16>>,
200 CCIfType<[i16], CCAssignToReg<RC.GPR_16>>,
243 // the way LLVM does multiple return values -- a return of {i16,i8} would end
246 // values into an i16 (which uses AX, and thus AL:AH).
253 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
320 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
349 CCIfType<[i8, i16], CCPromoteToType<i32>>,
[all …]

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