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Searched refs:hsub (Results 1 – 12 of 12) sorted by relevance

/freebsd/sys/arm/nvidia/drm2/
H A Dtegra_fb.c270 int hsub, vsub, i; in tegra_drm_fb_create() local
277 hsub = drm_format_horz_chroma_subsampling(cmd->pixel_format); in tegra_drm_fb_create()
285 width /= hsub; in tegra_drm_fb_create()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrGISel.td390 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
398 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
437 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
447 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
551 defm : VecStoreLane64_0Pat<am_indexed16, store, v4i16, i16, hsub, uimm12s2, STRHui>;
554 defm : VecStoreULane64_0Pat<store, v4i16, i16, hsub, STURHi>;
556 defm : VecROStoreLane64_0Pat<ro16, store, v4i16, i16, hsub, STRHroW, STRHroX>;
H A DAArch64InstrInfo.td3330 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
3331 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
3333 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
3334 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
3496 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
3500 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
3919 am_indexed16, am_unscaled16, uimm12s2, hsub>;
3925 am_indexed16, am_unscaled16, uimm12s2, hsub>;
3927 am_indexed16, am_unscaled16, uimm12s2, hsub>;
4169 defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, f16, hsub, STRHroW, STRHroX>;
[all …]
H A DAArch64SVEInstrInfo.td821 (DUP_ZZI_H (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), 0)>;
823 (DUP_ZZI_H (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), 0)>;
825 (DUP_ZZI_H (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), 0)>;
833 (DUP_ZZI_H (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), 0)>;
835 (DUP_ZZI_H (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), 0)>;
837 (DUP_ZZI_H (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), 0)>;
1988 (LASTB_VPZ_H (PTRUE_H 31), ZPR:$Z1), hsub))>;
3178 (INSERT_SUBREG (nxv8f16 (IMPLICIT_DEF)), FPR16:$src, hsub)>;
3180 (INSERT_SUBREG (nxv4f16 (IMPLICIT_DEF)), FPR16:$src, hsub)>;
3182 (INSERT_SUBREG (nxv2f16 (IMPLICIT_DEF)), FPR16:$src, hsub)>;
[all …]
H A DAArch64RegisterInfo.cpp233 if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub) in getSubClassWithSubReg()
235 else if (RC == &AArch64::GPR64allRegClass && Idx == AArch64::hsub) in getSubClassWithSubReg()
H A DAArch64RegisterInfo.td25 def hsub : SubRegIndex<16>;
347 let SubRegIndices = [hsub] in {
H A DAArch64InstrFormats.td5526 FPR16:$Rn, (f16 (EXTRACT_SUBREG V128:$Rm, hsub)), FPR16:$Ra)>;
5532 (f16 (EXTRACT_SUBREG V128:$Rn, hsub)), FPR16:$Rm, FPR16:$Ra)>;
8929 (f16 (EXTRACT_SUBREG V128:$Rn, hsub)), V128:$Rm, VectorIndexH:$idx)>;
8958 (SUBREG_TO_REG (i32 0), (f16 FPR16Op_lo:$Rm), hsub), (i64 0))>;
8968 (SUBREG_TO_REG (i32 0), (f16 FPR16Op_lo:$Rm), hsub), (i64 0))>;
9485 (f16 (EXTRACT_SUBREG V64:$Rn, hsub)),
9498 (f16 (EXTRACT_SUBREG V64:$Rn, hsub)),
H A DAArch64ISelLowering.cpp4349 SDValue Result = DAG.getTargetExtractSubreg(AArch64::hsub, dl, VT, Narrow); in LowerFP_ROUND()
4946 return DAG.getTargetExtractSubreg(AArch64::hsub, DL, OpVT, Op); in LowerBITCAST()
10001 SetVecVal(AArch64::hsub); in LowerFCOPYSIGN()
10022 return DAG.getTargetExtractSubreg(AArch64::hsub, DL, VT, BSP); in LowerFCOPYSIGN()
10768 TVal = DAG.getTargetInsertSubreg(AArch64::hsub, DL, MVT::f32, in LowerSELECT()
10770 FVal = DAG.getTargetInsertSubreg(AArch64::hsub, DL, MVT::f32, in LowerSELECT()
10777 return DAG.getTargetExtractSubreg(AArch64::hsub, DL, Ty, Res); in LowerSELECT()
25845 Op = DAG.getTargetInsertSubreg(AArch64::hsub, DL, MVT::f32, in ReplaceBITCASTResults()
H A DAArch64InstrInfo.cpp4734 RI.getMatchingSuperReg(DestReg, AArch64::hsub, &AArch64::FPR32RegClass); in copyPhysReg()
4736 RI.getMatchingSuperReg(SrcReg, AArch64::hsub, &AArch64::FPR32RegClass); in copyPhysReg()
H A DSVEInstrFormats.td1713 (!cast<Instruction>(NAME # _H) $Zn, (INSERT_SUBREG (IMPLICIT_DEF), $Vm, hsub))>;
1720 (!cast<Instruction>(NAME # _H) $Zn, (INSERT_SUBREG (IMPLICIT_DEF), $Vm, hsub))>;
/freebsd/sys/dev/drm2/
H A Ddrm_crtc.c2247 int ret, hsub, vsub, num_planes, i; in framebuffer_check() local
2255 hsub = drm_format_horz_chroma_subsampling(r->pixel_format); in framebuffer_check()
2259 if (r->width == 0 || r->width % hsub) { in framebuffer_check()
2270 unsigned int width = r->width / (i != 0 ? hsub : 1); in framebuffer_check()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp656 SubReg = AArch64::hsub; in getSubRegForClass()
3750 return BuildFn(AArch64::hsub); in emitScalarToVector()
3865 ExtractSubReg = AArch64::hsub; in getLaneCopyOpcode()
4236 SubregIdx = AArch64::hsub; in getInsertVecEltOpInfo()