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Searched refs:hsub (Results 1 – 13 of 13) sorted by relevance

/freebsd/sys/arm/nvidia/drm2/
H A Dtegra_fb.c270 int hsub, vsub, i; in tegra_drm_fb_create() local
277 hsub = drm_format_horz_chroma_subsampling(cmd->pixel_format); in tegra_drm_fb_create()
285 width /= hsub; in tegra_drm_fb_create()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrGISel.td333 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
341 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
380 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
390 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
494 defm : VecStoreLane64_0Pat<am_indexed16, store, v4i16, i16, hsub, uimm12s2, STRHui>;
497 defm : VecStoreULane64_0Pat<store, v4i16, i16, hsub, STURHi>;
499 defm : VecROStoreLane64_0Pat<ro16, store, v4i16, i16, hsub, STRHroW, STRHroX>;
H A DAArch64InstrInfo.td4257 ro16, am_indexed16, am_unscaled16, uimm12s2, hsub>;
4266 ro16, am_indexed16, am_unscaled16, uimm12s2, hsub>;
4269 ro16, am_indexed16, am_unscaled16, uimm12s2, hsub>;
4555 defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, f16, hsub, STRHroW, STRHroX>;
4556 defm : VecROStoreLane0Pat<ro16, store, v8f16, f16, f16, hsub, STRHroW, STRHroX>;
4691 defm : VecStoreLane0Pat<am_indexed16, truncstorei16, v8i16, i32, f16, hsub, uimm12s2, STRHui>;
4692 defm : VecStoreLane0Pat<am_indexed16, store, v8f16, f16, f16, hsub, uimm12s2, STRHui>;
4844 defm : VecStoreULane0Pat<truncstorei16, v8i16, i32, f16, hsub, STURHi>;
4845 defm : VecStoreULane0Pat<store, v8f16, f16, f16, hsub, STURHi>;
5467 FPR16:$Rn, (f16 (EXTRACT_SUBREG V128:$Rm, hsub)))>;
[all …]
H A DAArch64SVEInstrInfo.td934 (DUP_ZZI_H (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), 0)>;
936 (DUP_ZZI_H (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), 0)>;
938 (DUP_ZZI_H (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), 0)>;
946 (DUP_ZZI_H (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), 0)>;
948 (DUP_ZZI_H (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), 0)>;
950 (DUP_ZZI_H (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), 0)>;
2125 (LASTB_VPZ_H (PTRUE_H 31), ZPR:$Z1), hsub))>;
3325 (INSERT_SUBREG (nxv8f16 (IMPLICIT_DEF)), FPR16:$src, hsub)>;
3327 (INSERT_SUBREG (nxv4f16 (IMPLICIT_DEF)), FPR16:$src, hsub)>;
3329 (INSERT_SUBREG (nxv2f16 (IMPLICIT_DEF)), FPR16:$src, hsub)>;
[all …]
H A DAArch64RegisterInfo.cpp243 if (RC == &AArch64::GPR32allRegClass && Idx == AArch64::hsub) in getSubClassWithSubReg()
245 else if (RC == &AArch64::GPR64allRegClass && Idx == AArch64::hsub) in getSubClassWithSubReg()
H A DAArch64RegisterInfo.td31 def hsub : SubRegIndex<16, 0>;
43 // * H0 is described with 'bsub + bsub_hi' == 'hsub'.
395 let SubRegIndices = [hsub, hsub_hi] in {
H A DAArch64InstrFormats.td5879 FPR16:$Rn, (f16 (EXTRACT_SUBREG V128:$Rm, hsub)), FPR16:$Ra)>;
5885 (f16 (EXTRACT_SUBREG V128:$Rn, hsub)), FPR16:$Rm, FPR16:$Ra)>;
5891 (f16 (EXTRACT_SUBREG V128:$Rn, hsub)),
5892 (f16 (EXTRACT_SUBREG V128:$Rm, hsub)), FPR16:$Ra)>;
9351 (f16 (EXTRACT_SUBREG V128:$Rn, hsub)), V128:$Rm, VectorIndexH:$idx)>;
9380 (SUBREG_TO_REG (i32 0), (f16 FPR16Op_lo:$Rm), hsub), (i64 0))>;
9390 (SUBREG_TO_REG (i32 0), (f16 FPR16Op_lo:$Rm), hsub), (i64 0))>;
9400 (f16 (EXTRACT_SUBREG V128:$Rn, hsub)), V128_lo:$Rm, VectorIndexH:$idx)>;
9923 (f16 (EXTRACT_SUBREG V64:$Rn, hsub)),
9936 (f16 (EXTRACT_SUBREG V64:$Rn, hsub)),
H A DAArch64InstrInfo.cpp5341 MCRegister DestRegD = TRI->getMatchingSuperReg(DestReg, AArch64::hsub, in copyPhysReg()
5343 MCRegister SrcRegD = TRI->getMatchingSuperReg(SrcReg, AArch64::hsub, in copyPhysReg()
5353 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub, in copyPhysReg()
5355 SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub, in copyPhysReg()
H A DAArch64ISelLowering.cpp4477 SDValue Result = DAG.getTargetExtractSubreg(AArch64::hsub, DL, VT, Narrow); in LowerFP_ROUND()
5158 return DAG.getTargetExtractSubreg(AArch64::hsub, DL, OpVT, Op); in LowerBITCAST()
10664 SetVecVal(AArch64::hsub); in LowerFCOPYSIGN()
10685 return DAG.getTargetExtractSubreg(AArch64::hsub, DL, VT, BSP); in LowerFCOPYSIGN()
11596 TVal = DAG.getTargetInsertSubreg(AArch64::hsub, DL, MVT::f32, in LowerSELECT()
11598 FVal = DAG.getTargetInsertSubreg(AArch64::hsub, DL, MVT::f32, in LowerSELECT()
11606 return DAG.getTargetExtractSubreg(AArch64::hsub, DL, Ty, Res); in LowerSELECT()
23970 return AArch64::hsub; in getFPSubregForVT()
27324 Op = DAG.getTargetInsertSubreg(AArch64::hsub, DL, MVT::f32, in ReplaceBITCASTResults()
H A DSVEInstrFormats.td1848 (!cast<Instruction>(NAME # _H) $Zn, (INSERT_SUBREG (IMPLICIT_DEF), $Vm, hsub))>;
1855 (!cast<Instruction>(NAME # _H) $Zn, (INSERT_SUBREG (IMPLICIT_DEF), $Vm, hsub))>;
/freebsd/sys/dev/drm2/
H A Ddrm_crtc.c2247 int ret, hsub, vsub, num_planes, i; in framebuffer_check() local
2255 hsub = drm_format_horz_chroma_subsampling(r->pixel_format); in framebuffer_check()
2259 if (r->width == 0 || r->width % hsub) { in framebuffer_check()
2270 unsigned int width = r->width / (i != 0 ? hsub : 1); in framebuffer_check()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp663 SubReg = AArch64::hsub; in getSubRegForClass()
3885 return BuildFn(AArch64::hsub); in emitScalarToVector()
4000 ExtractSubReg = AArch64::hsub; in getLaneCopyOpcode()
4371 SubregIdx = AArch64::hsub; in getInsertVecEltOpInfo()
5595 InsertIntoSubReg = AArch64::hsub; in selectIndexedExtLoad()
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltinsX86.td111 foreach Op = ["addsub", "hadd", "hsub"] in {
135 foreach Op = ["addsub", "hadd", "hsub", "max", "min"] in {