Searched refs:hasSuperClassEq (Results 1 – 17 of 17) sorted by relevance
139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()271 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()514 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || in optimizeAllLanesPattern()515 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { in optimizeAllLanesPattern()531 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { in optimizeAllLanesPattern()537 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && in optimizeAllLanesPattern()
149 assert((RC->hasSuperClassEq(&ARM::tGPRRegClass) || in loadRegFromStackSlot()153 if (RC->hasSuperClassEq(&ARM::tGPRRegClass) || in loadRegFromStackSlot()
109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()116 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()118 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
3468 if (RC->hasSuperClassEq(&AArch64::GPR64RegClass)) { in emitLdStWithAddr()
1658 if (!Subtarget->hasVLX() && (OpRC->hasSuperClassEq(&X86::VR128RegClass) || in hardenLoadAddr()1659 OpRC->hasSuperClassEq(&X86::VR256RegClass))) { in hardenLoadAddr()1661 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128RegClass); in hardenLoadAddr()1695 } else if (OpRC->hasSuperClassEq(&X86::VR128XRegClass) || in hardenLoadAddr()1696 OpRC->hasSuperClassEq(&X86::VR256XRegClass) || in hardenLoadAddr()1697 OpRC->hasSuperClassEq(&X86::VR512RegClass)) { in hardenLoadAddr()1699 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128XRegClass); in hardenLoadAddr()1700 bool Is256Bit = OpRC->hasSuperClassEq(&X86::VR256XRegClass); in hardenLoadAddr()1728 assert(OpRC->hasSuperClassEq(&X86::GR64RegClass) && in hardenLoadAddr()1886 return RC->hasSuperClassEq(GPRRegClasses[RegIdx]); in canHardenRegister()
228 if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 && in shouldRewriteCopySrc()229 SrcRC->hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit) in shouldRewriteCopySrc()
58704 return RC.hasSuperClassEq(&X86::GR8RegClass) || in isGRClass()58705 RC.hasSuperClassEq(&X86::GR16RegClass) || in isGRClass()58706 RC.hasSuperClassEq(&X86::GR32RegClass) || in isGRClass()58707 RC.hasSuperClassEq(&X86::GR64RegClass) || in isGRClass()58708 RC.hasSuperClassEq(&X86::LOW32_ADDR_ACCESS_RBPRegClass); in isGRClass()58714 return RC.hasSuperClassEq(&X86::FR16XRegClass) || in isFRClass()58715 RC.hasSuperClassEq(&X86::FR32XRegClass) || in isFRClass()58716 RC.hasSuperClassEq(&X86::FR64XRegClass) || in isFRClass()58717 RC.hasSuperClassEq(&X86::VR128XRegClass) || in isFRClass()58718 RC.hasSuperClassEq(&X86::VR256XRegClass) || in isFRClass()[all …]
470 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitLoad()490 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && in PPCEmitLoad()624 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitStore()1283 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); in SelectBinaryIntOp()2126 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCMaterialize32BitInt()
184 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()185 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()5092 MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ? in transformToImmFormFedByLI()
389 if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) && in shouldCoalesce()
143 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq() function
187 return SrcRC->hasSuperClassEq(DstRC) || SrcRC->hasSubClassEq(DstRC); in isTransientMI()
480 if (RCA && RCA->hasSuperClassEq(RCS)) in PerformSinkAndFold()482 else if (RCB && RCB->hasSuperClassEq(RCS)) in PerformSinkAndFold()
2640 if (!RC->hasSuperClassEq(DRC)) { in visitMachineOperand()
3231 return RC.hasSuperClassEq(getVGPRClassForBitWidth(getRegSizeInBits(RC))); in isProperlyAlignedRC()3233 return RC.hasSuperClassEq(getAGPRClassForBitWidth(getRegSizeInBits(RC))); in isProperlyAlignedRC()3235 return RC.hasSuperClassEq( in isProperlyAlignedRC()
1193 if (RegClass->hasSuperClassEq(&AMDGPU::VReg_64RegClass)) { in materializeImmediate()5715 return RC->hasSuperClassEq(DRC); in isLegalRegOperand()9520 if (RC->hasSuperClassEq(&AMDGPU::SReg_32RegClass)) { in foldMemoryOperandImpl()9524 if (RC->hasSuperClassEq(&AMDGPU::SReg_64RegClass)) { in foldMemoryOperandImpl()
92 RC->hasSuperClassEq(TRI.getBoolRC()); in isVCC()