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Searched refs:has16BitInsts (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetTransformInfo.cpp352 return (ElemWidth == 8 && ST->has16BitInsts()) ? 4 in getMaximumVF()
353 : (ElemWidth == 16 && ST->has16BitInsts()) ? 2 in getMaximumVF()
552 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
567 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
578 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()
594 if (ST->has16BitInsts() && SLT == MVT::f16 && !HasFP64FP16Denormals) in getArithmeticInstrCost()
613 if (ST->has16BitInsts() && SLT == MVT::f16) in getArithmeticInstrCost()
637 (SLT == MVT::f16 && ST->has16BitInsts())) { in getArithmeticInstrCost()
642 if (SLT == MVT::f16 && ST->has16BitInsts()) { in getArithmeticInstrCost()
893 if (EltSize == 16 && Index == 0 && ST->has16BitInsts()) in getVectorInstrCost()
H A DAMDGPUSubtarget.h191 bool has16BitInsts() const { in has16BitInsts() function
H A DAMDGPUCodeGenPrepare.cpp431 (Ty->isHalfTy() && ST.has16BitInsts()); in isLegalFloatingTy()
639 if (Size <= 16 && ST.has16BitInsts()) in replaceMulWithMul24()
1638 if (ST.has16BitInsts() && needsPromotionToI32(I.getType()) && in visitBinaryOperator()
1776 if (ST.has16BitInsts() && needsPromotionToI32(I.getOperand(0)->getType()) && in visitICmpInst()
1790 if (ST.has16BitInsts() && needsPromotionToI32(I.getType())) { in visitSelectInst()
2215 if (ST.has16BitInsts() && needsPromotionToI32(I.getType()) && in visitBitreverseIntrinsicInst()
2315 if (!Ty->isFloatTy() && (!Ty->isHalfTy() || ST.has16BitInsts())) in visitSqrt()
H A DAMDGPULegalizerInfo.cpp713 const LLT MinScalarFPTy = ST.has16BitInsts() ? S16 : S32; in AMDGPULegalizerInfo()
780 } else if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()
945 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()
970 } else if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()
985 .clampScalar(0, ST.has16BitInsts() ? S16 : S32, S64); in AMDGPULegalizerInfo()
989 .clampScalar(0, ST.has16BitInsts() ? S16 : S32, S64); in AMDGPULegalizerInfo()
993 .clampScalar(0, ST.has16BitInsts() ? S16 : S32, S64); in AMDGPULegalizerInfo()
1001 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()
1073 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()
1103 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()
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H A DAMDGPUISelLowering.cpp417 if (Subtarget->has16BitInsts()) { in AMDGPUTargetLowering()
429 if (Subtarget->has16BitInsts()) { in AMDGPUTargetLowering()
822 (ScalarVT == MVT::f16 && Subtarget->has16BitInsts())); in isFPImmLegal()
967 (Subtarget->has16BitInsts() && (VT == MVT::f16 || VT == MVT::bf16)); in isFAbsFree()
1010 if (DestSize== 16 && Subtarget->has16BitInsts()) in isTruncateFree()
1020 if (SrcSize == 16 && Subtarget->has16BitInsts()) in isZExtFree()
1056 if (Subtarget->has16BitInsts() && in isNarrowingProfitable()
2720 assert(!Subtarget->has16BitInsts()); in LowerFLOG2()
2761 if (VT == MVT::f16 && !Subtarget->has16BitInsts()) { in LowerFLOGCommon()
2767 if (VT == MVT::f16 && !Subtarget->has16BitInsts()) { in LowerFLOGCommon()
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H A DSIISelLowering.cpp158 if (Subtarget->has16BitInsts()) { in SITargetLowering()
489 if (Subtarget->has16BitInsts()) { in SITargetLowering()
567 if (Subtarget->has16BitInsts()) { in SITargetLowering()
850 if (Subtarget->has16BitInsts()) { in SITargetLowering()
993 if (Subtarget->has16BitInsts() && !Subtarget->hasMed3_16()) in SITargetLowering()
1080 if (Subtarget->has16BitInsts()) { in getRegisterTypeForCallingConv()
1089 return Subtarget->has16BitInsts() ? MVT::i16 : MVT::i32; in getRegisterTypeForCallingConv()
1111 if (Size == 16 && Subtarget->has16BitInsts()) in getNumRegistersForCallingConv()
1135 if (Size == 16 && Subtarget->has16BitInsts()) { in getVectorTypeBreakdownForCallingConv()
1154 if (Size < 16 && Subtarget->has16BitInsts()) { in getVectorTypeBreakdownForCallingConv()
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H A DSIInstrInfo.cpp4364 return ST.has16BitInsts() && in isInlineConstant()
4383 return ST.has16BitInsts() && in isInlineConstant()
4386 return ST.has16BitInsts() && in isInlineConstant()
4445 return ST.has16BitInsts() && in isInlineConstant()
4455 return ST.has16BitInsts() && in isInlineConstant()
H A DAMDGPU.td2432 def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
H A DAMDGPUInstructionSelector.cpp1204 if (Size == 16 && !ST.has16BitInsts()) in getV_CMPOpcode()