| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 859 Victim = DAG.getZeroExtendInReg(Victim, dl, MVT::i8); in LowerShifts()
869 : DAG.getZeroExtendInReg(Victim, dl, MVT::i8); in LowerShifts()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 1076 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT); in lowerPrivateTruncStore()
1310 Ret = DAG.getZeroExtendInReg(Ret, DL, MemEltVT); in lowerPrivateExtLoad()
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| H A D | AMDGPUISelLowering.cpp | 5431 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT); in PerformDAGCombine()
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| H A D | SIISelLowering.cpp | 10897 Cvt = DAG.getZeroExtendInReg(NewLoad, SL, TruncVT); in widenLoad()
14494 DAG.getZeroExtendInReg(AddRHS, SL, MVT::i32), false); in tryFoldMADwithSRL()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 554 Value = DAG.getZeroExtendInReg(Value, dl, StVT); in LegalizeStoreOps()
949 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); in LegalizeLoadOps()
3227 RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType); in ExpandNode()
3231 LHS = DAG.getZeroExtendInReg(Res, dl, AtomicType); in ExpandNode()
3232 RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType); in ExpandNode()
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| H A D | LegalizeIntegerTypes.cpp | 949 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType()); in PromoteIntRes_INT_EXTEND()
1603 Lo = DAG.getZeroExtendInReg(Lo, DL, OldVT); in PromoteIntRes_FunnelShift()
1767 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT); in PromoteIntRes_UADDSUBO()
2623 return DAG.getZeroExtendInReg(Op, dl, Src.getValueType()); in PromoteIntOp_ZERO_EXTEND()
5387 Hi = DAG.getZeroExtendInReg(Hi, dl, in ExpandIntRes_ZERO_EXTEND()
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| H A D | LegalizeTypes.h | 273 return DAG.getZeroExtendInReg(Op, dl, OldVT); in ZExtPromotedInteger()
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| H A D | DAGCombiner.cpp | 1550 return DAG.getZeroExtendInReg(NewOp, DL, OldVT); in ZExtPromoteOperand()
14811 Op = DAG.getZeroExtendInReg(Op, DL, MinVT); in visitZERO_EXTEND()
14823 SDValue And = DAG.getZeroExtendInReg(Op, DL, MinVT); in visitZERO_EXTEND()
14955 return DAG.getZeroExtendInReg(VSetCC, DL, N0.getValueType()); in visitZERO_EXTEND()
14965 return DAG.getZeroExtendInReg(DAG.getAnyExtOrTrunc(VsetCC, DL, VT), DL, in visitZERO_EXTEND()
15648 return DAG.getZeroExtendInReg(N0, DL, ExtVT); in visitSIGN_EXTEND_INREG()
23410 NewVal = DAG.getZeroExtendInReg(NewVal, DL, MVT::i1); in scalarizeExtractedBinOp()
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| H A D | SelectionDAG.cpp | 1563 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) { in getZeroExtendInReg() function in SelectionDAG
1609 return getZeroExtendInReg(Op, DL, VT); in getPtrExtendInReg()
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| H A D | TargetLowering.cpp | 2457 return TLO.CombineTo(Op, TLO.DAG.getZeroExtendInReg(Op0, dl, ExVT)); in SimplifyDemandedBits()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 2614 Vs[i] = DAG.getZeroExtendInReg(Vs[i], dl, MVT::i8); in buildVector32()
2722 ExtV = DAG.getZeroExtendInReg(VecV, dl, tyScalar(ValTy)); in extractVector()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAG.h | 1067 LLVM_ABI SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 21140 In = DAG.getZeroExtendInReg(In, DL, DstVT); in truncateVectorWithPACKUS()
25544 StoredVal = DAG.getZeroExtendInReg( in LowerStore()
50937 return DAG.getZeroExtendInReg(Op, DL, NarrowVT); in PromoteMaskArithmetic()
53340 Val = DAG.getZeroExtendInReg(Val, dl, MVT::i1); in combineStore()
54140 return DAG.getZeroExtendInReg(NewOpNode, DL, CleanUpVT); in combinei64TruncSrlConstant()
55769 Res = DAG.getZeroExtendInReg(Res, dl, N0.getValueType()); in combineExtSetcc()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 3102 FpToInt = DAG.getZeroExtendInReg(FpToInt, DL, MVT::i32); in lowerFP_TO_INT_SAT()
17774 FpToInt = DAG.getZeroExtendInReg(FpToInt, DL, MVT::i32); in performFP_TO_INT_SATCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 18862 : DAG.getZeroExtendInReg(VVT, DL, ExtVT); in PerformMVEExtCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 6743 SDValue Trunc = DAG.getZeroExtendInReg(Ext, DL, DestVT); in LowerADDRSPACECAST()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Testing/Demangle/ |
| H A D | DemangleTestCases.inc | 15040 …tendInRegENS_7SDValueENS_8DebugLocENS_3EVTE", "llvm::SelectionDAG::getZeroExtendInReg(llvm::SDValu…
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