Home
last modified time | relevance | path

Searched refs:getXLen (Results 1 – 22 of 22) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInterleavedAccess.cpp98 auto *XLenTy = Type::getIntNTy(LI->getContext(), Subtarget.getXLen()); in lowerInterleavedLoad()
178 auto *XLenTy = Type::getIntNTy(SI->getContext(), Subtarget.getXLen()); in lowerInterleavedStore()
256 Type *XLenTy = Type::getIntNTy(LI->getContext(), Subtarget.getXLen()); in lowerDeinterleaveIntrinsicToLoad()
326 Type *XLenTy = Type::getIntNTy(SI->getContext(), Subtarget.getXLen()); in lowerInterleaveIntrinsicToStore()
450 auto *XLenTy = Type::getIntNTy(Load->getContext(), Subtarget.getXLen()); in lowerInterleavedVPLoad()
559 auto *XLenTy = Type::getIntNTy(Store->getContext(), Subtarget.getXLen()); in lowerInterleavedVPStore()
H A DRISCVOptWInstrs.cpp206 if (Bits >= (ST.getXLen() / 2)) in hasAllNBitUsers()
226 if (Bits >= (ST.getXLen() - ShAmt)) in hasAllNBitUsers()
260 if (Bits >= Log2_32(ST.getXLen())) in hasAllNBitUsers()
272 if (OpIdx == 2 && Bits >= Log2_32(ST.getXLen())) in hasAllNBitUsers()
H A DRISCVCodeGenPrepare.cpp257 if (II.getType()->getScalarSizeInBits() > ST->getXLen()) in expandVPStrideLoad()
H A DRISCVISelDAGToDAG.cpp1187 unsigned XLen = Subtarget->getXLen(); in Select()
1237 unsigned XLen = Subtarget->getXLen(); in Select()
1292 unsigned LShAmt = Subtarget->getXLen() - TrailingOnes; in Select()
1329 unsigned LShAmt = Subtarget->getXLen() - ExtSize; in Select()
1366 unsigned XLen = Subtarget->getXLen(); in Select()
1594 unsigned XLen = Subtarget->getXLen(); in Select()
1704 unsigned XLen = Subtarget->getXLen(); in Select()
3315 unsigned XLen = Subtarget->getXLen(); in selectSHXADDOp()
3370 unsigned XLen = Subtarget->getXLen(); in selectSHXADDOp()
3397 unsigned XLen = Subtarget->getXLen(); in selectSHXADDOp()
[all …]
H A DRISCVSubtarget.h199 unsigned getXLen() const { in getXLen() function
H A DRISCVFrameLowering.cpp129 int64_t SlotSize = STI.getXLen() / 8; in emitSCSPrologue()
188 int64_t SlotSize = STI.getXLen() / 8; in emitSCSEpilogue()
964 alignTo((STI.getXLen() / 8) * LibCallRegs, getStackAlign()); in emitPrologue()
1880 const uint64_t RVCompressLen = STI.getXLen() * 8; in getFirstSPAdjustAmount()
1944 RVFI->setRVPushStackSize(alignTo((STI.getXLen() / 8) * PushedRegNum, 16)); in assignCalleeSavedSpillSlots()
2023 alignTo((STI.getXLen() / 8) * LibCallRegs, getStackAlign()); in assignCalleeSavedSpillSlots()
H A DRISCVISelDAGToDAG.h91 return selectShiftMask(N, Subtarget->getXLen(), ShAmt); in selectShiftMaskXLen()
H A DRISCVCallingConv.cpp333 unsigned XLen = Subtarget.getXLen(); in CC_RISCV()
688 if (LocVT.getSizeInBits() != Subtarget.getXLen()) { in CC_RISCV_FastCC()
H A DRISCVTargetTransformInfo.cpp223 if (Inst && Idx == 1 && Imm.getBitWidth() <= ST->getXLen() && in getIntImmCostInst()
352 return TypeSize::getFixed(ST->getXLen()); in getRegisterBitWidth()
2332 ST->getXLen() < Val->getScalarSizeInBits()) { in getVectorInstrCost()
2953 unsigned MinSize = ST->getXLen() / 8 + 1; in enableMemCmpExpansion()
H A DRISCVISelLowering.cpp692 setMaxAtomicSizeInBitsSupported(Subtarget.getXLen()); in RISCVTargetLowering()
698 setMaxAtomicSizeInBitsSupported(Subtarget.getXLen()); in RISCVTargetLowering()
2199 if (BitSize > Subtarget.getXLen()) in shouldConvertConstantLoadToIntImm()
2320 if (Subtarget.getXLen() < VT.getScalarSizeInBits()) { in isFPImmLegal()
2335 Subtarget.getXLen(), Subtarget); in isFPImmLegal()
3966 unsigned NumViaIntegerBits = std::clamp(NumElts, 8u, Subtarget.getXLen()); in lowerBuildVectorOfConstants()
4210 if (ElemSizeInBits >= std::min(Subtarget.getELen(), Subtarget.getXLen()) || in lowerBuildVectorViaPacking()
6882 Mask = Mask.sext(Subtarget.getXLen()); in lowerFABSorFNEG()
6906 if (SignSize == Subtarget.getXLen()) in lowerFCOPYSIGN()
6934 APInt::getSignMask(16).sext(Subtarget.getXLen()), DL, XLenVT); in lowerFCOPYSIGN()
[all …]
H A DRISCVInstrInfo.cpp617 assert(STI.getXLen() == 64 && "Unexpected GPR size"); in copyPhysReg()
625 assert(STI.getXLen() == 64 && "Unexpected GPR size"); in copyPhysReg()
846 if (ST.getXLen() < (1U << Log2SEW)) in getFoldedOpcode()
1602 unsigned XLen = STI.getXLen(); in isBranchOffsetInRange()
H A DRISCVInstrInfoZb.td131 return (unsigned)llvm::popcount(N->getZExtValue()) == Subtarget->getXLen() - 2;
H A DRISCVInstrInfo.td527 uint64_t XLen = Subtarget->getXLen();
578 uint64_t XLen = Subtarget->getXLen();
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp66 LLT p0 = LLT::pointer(0, Subtarget.getXLen()); in getStackAddress()
67 LLT sXLen = LLT::scalar(Subtarget.getXLen()); in getStackAddress()
220 return MIRBuilder.buildFrameIndex(LLT::pointer(0, Subtarget.getXLen()), FI) in getStackAddress()
470 unsigned XLenInBytes = Subtarget.getXLen() / 8; in saveVarArgRegisters()
501 Subtarget.getXLen()); in saveVarArgRegisters()
502 const LLT sXLen = LLT::scalar(Subtarget.getXLen()); in saveVarArgRegisters()
H A DRISCVInstructionSelector.cpp99 return selectShiftMask(Root, STI.getXLen()); in selectShiftMaskXLen()
236 if (OpIdx == 2 && Bits >= Log2_32(Subtarget->getXLen())) in hasAllNBitUsers()
241 if (Bits >= Subtarget->getXLen() - UserMI.getOperand(2).getImm()) in hasAllNBitUsers()
403 const unsigned XLen = STI.getXLen(); in selectSHXADDOp()
856 const LLT sXLen = LLT::scalar(STI.getXLen()); in replacePtrWithInt()
868 const LLT sXLen = LLT::scalar(STI.getXLen()); in preISelLower()
877 const LLT sXLen = LLT::scalar(STI.getXLen()); in preISelLower()
901 MIB.addImm(STI.getXLen() - CstVal); in renderImmSubFromXLen()
944 MIB.addImm(Subtarget->getXLen() - llvm::countr_one(C)); in renderXLenSubTrailingOnes()
H A DRISCVLegalizerInfo.cpp75 : STI(ST), XLen(STI.getXLen()), sXLen(LLT::scalar(XLen)) { in RISCVLegalizerInfo()
589 (Query.Types[1].getSizeInBits() < ST.getXLen()) && in RISCVLegalizerInfo()
/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DRISCVISAInfo.h61 unsigned getXLen() const { return XLen; } in getXLen() function
/freebsd/contrib/llvm-project/llvm/lib/Object/
H A DELFObjectFile.cpp388 if (ISAInfo->getXLen() == 32) in getRISCVFeatures()
390 else if (ISAInfo->getXLen() == 64) in getRISCVFeatures()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp3008 if (ISAInfo->getXLen() == 32 && isRV64()) in resetToArch()
3010 else if (ISAInfo->getXLen() == 64 && !isRV64()) in resetToArch()
3014 if (ISAInfo->getXLen() == 32) in resetToArch()
3016 else if (ISAInfo->getXLen() == 64) in resetToArch()
/freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/
H A DGnu.cpp1636 addMultilibFlag(ISAInfo->getXLen() == 32, "-m32", NewFlags); in selectRISCVMultilib()
1637 addMultilibFlag(ISAInfo->getXLen() == 64, "-m64", NewFlags); in selectRISCVMultilib()
1687 if (MLConfigISAInfo->getXLen() == 32) { in selectRISCVMultilib()
/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DRISCV.cpp1104 mergedXlen = info.getXLen(); in mergeArch()
/freebsd/contrib/llvm-project/clang/lib/Driver/
H A DDriver.cpp843 unsigned XLen = (*ISAInfo)->getXLen(); in computeTargetTriple()