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Searched refs:getXLen (Results 1 – 20 of 20) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp74 LLT p0 = LLT::pointer(0, Subtarget.getXLen()); in getStackAddress()
75 LLT sXLen = LLT::scalar(Subtarget.getXLen()); in getStackAddress()
226 return MIRBuilder.buildFrameIndex(LLT::pointer(0, Subtarget.getXLen()), FI) in getStackAddress()
366 return T->getIntegerBitWidth() <= Subtarget.getXLen() * 2; in isSupportedReturnType()
444 unsigned XLenInBytes = Subtarget.getXLen() / 8; in saveVarArgRegisters()
475 Subtarget.getXLen()); in saveVarArgRegisters()
476 const LLT sXLen = LLT::scalar(Subtarget.getXLen()); in saveVarArgRegisters()
H A DRISCVInstructionSelector.cpp253 const unsigned XLen = STI.getXLen(); in selectSHXADDOp()
762 const LLT sXLen = LLT::scalar(STI.getXLen()); in replacePtrWithInt()
775 const LLT sXLen = LLT::scalar(STI.getXLen()); in preISelLower()
784 const LLT sXLen = LLT::scalar(STI.getXLen()); in preISelLower()
807 MIB.addImm(STI.getXLen() - CstVal); in renderImmSubFromXLen()
H A DRISCVLegalizerInfo.cpp71 : STI(ST), XLen(STI.getXLen()), sXLen(LLT::scalar(XLen)) { in RISCVLegalizerInfo()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVOptWInstrs.cpp200 if (Bits >= (ST.getXLen() / 2)) in hasAllNBitUsers()
219 if (Bits >= (ST.getXLen() - UserMI->getOperand(2).getImm())) in hasAllNBitUsers()
244 if (Bits >= Log2_32(ST.getXLen())) in hasAllNBitUsers()
256 if (OpIdx == 2 && Bits >= Log2_32(ST.getXLen())) in hasAllNBitUsers()
H A DRISCVFrameLowering.cpp84 int64_t SlotSize = STI.getXLen() / 8; in emitSCSPrologue()
144 int64_t SlotSize = STI.getXLen() / 8; in emitSCSEpilogue()
582 alignTo((STI.getXLen() / 8) * LibCallRegs, getStackAlign()); in emitPrologue()
1368 const uint64_t RVCompressLen = STI.getXLen() * 8; in getFirstSPAdjustAmount()
1414 RVFI->setRVPushStackSize(alignTo((STI.getXLen() / 8) * PushedRegNum, 16)); in assignCalleeSavedSpillSlots()
1467 alignTo((STI.getXLen() / 8) * LibCallRegs, getStackAlign()); in assignCalleeSavedSpillSlots()
H A DRISCVCodeGenPrepare.cpp181 if (II.getType()->getScalarSizeInBits() > ST->getXLen()) in expandVPStrideLoad()
H A DRISCVSubtarget.h169 unsigned getXLen() const { in getXLen() function
H A DRISCVISelDAGToDAG.cpp1086 unsigned XLen = Subtarget->getXLen(); in Select()
1115 unsigned XLen = Subtarget->getXLen(); in Select()
1165 unsigned LShAmt = Subtarget->getXLen() - TrailingOnes; in Select()
1199 unsigned LShAmt = Subtarget->getXLen() - ExtSize; in Select()
1244 unsigned XLen = Subtarget->getXLen(); in Select()
1502 unsigned XLen = Subtarget->getXLen(); in Select()
2943 unsigned XLen = Subtarget->getXLen(); in selectSHXADDOp()
2990 unsigned XLen = Subtarget->getXLen(); in selectSHXADDOp()
3172 if (UI.getOperandNo() != 1 || Bits < Log2_32(Subtarget->getXLen())) in hasAllNBitUsers()
3177 if (Bits < Subtarget->getXLen() - User->getConstantOperandVal(1)) in hasAllNBitUsers()
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H A DRISCVISelDAGToDAG.h89 return selectShiftMask(N, Subtarget->getXLen(), ShAmt); in selectShiftMaskXLen()
H A DRISCVTargetTransformInfo.cpp214 if (Inst && Idx == 1 && Imm.getBitWidth() <= ST->getXLen() && in getIntImmCostInst()
322 return TypeSize::getFixed(ST->getXLen()); in getRegisterBitWidth()
1640 ST->getXLen() < Val->getScalarSizeInBits()) { in getVectorInstrCost()
H A DRISCVISelLowering.cpp646 setMaxAtomicSizeInBitsSupported(Subtarget.getXLen()); in RISCVTargetLowering()
652 setMaxAtomicSizeInBitsSupported(Subtarget.getXLen()); in RISCVTargetLowering()
2002 if (BitSize > Subtarget.getXLen()) in shouldConvertConstantLoadToIntImm()
2273 if (Subtarget.getXLen() < VT.getScalarSizeInBits()) { in isFPImmLegal()
2286 1 + RISCVMatInt::getIntMatCost(Imm.bitcastToAPInt(), Subtarget.getXLen(), in isFPImmLegal()
3652 unsigned NumViaIntegerBits = std::clamp(NumElts, 8u, Subtarget.getXLen()); in lowerBuildVectorOfConstants()
3957 if (ElemSizeInBits >= std::min(Subtarget.getELen(), Subtarget.getXLen()) || in lowerBuildVectorViaPacking()
7744 TrueVal, Subtarget.getXLen(), Subtarget, /*CompressionCost=*/true); in lowerSELECT()
7746 FalseVal, Subtarget.getXLen(), Subtarget, /*CompressionCost=*/true); in lowerSELECT()
7916 int XLenInBytes = Subtarget.getXLen() / in lowerFRAMEADDR()
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H A DRISCVInstrInfo.cpp528 assert(STI.getXLen() == 64 && "Unexpected GPR size"); in copyPhysReg()
536 assert(STI.getXLen() == 64 && "Unexpected GPR size"); in copyPhysReg()
1267 unsigned XLen = STI.getXLen(); in isBranchOffsetInRange()
H A DRISCVInstrInfoZb.td142 return (unsigned)llvm::popcount(N->getZExtValue()) == Subtarget->getXLen() - 2;
H A DRISCVInstrInfo.td418 uint64_t XLen = Subtarget->getXLen();
463 uint64_t XLen = Subtarget->getXLen();
/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DRISCVISAInfo.h60 unsigned getXLen() const { return XLen; } in getXLen() function
/freebsd/contrib/llvm-project/llvm/lib/Object/
H A DELFObjectFile.cpp387 if (ISAInfo->getXLen() == 32) in getRISCVFeatures()
389 else if (ISAInfo->getXLen() == 64) in getRISCVFeatures()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp2805 if (ISAInfo->getXLen() == 32 && isRV64()) in resetToArch()
2807 else if (ISAInfo->getXLen() == 64 && !isRV64()) in resetToArch()
2811 if (ISAInfo->getXLen() == 32) in resetToArch()
2813 else if (ISAInfo->getXLen() == 64) in resetToArch()
/freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/
H A DGnu.cpp1760 addMultilibFlag(ISAInfo->getXLen() == 32, "-m32", NewFlags); in selectRISCVMultilib()
1761 addMultilibFlag(ISAInfo->getXLen() == 64, "-m64", NewFlags); in selectRISCVMultilib()
1811 if (MLConfigISAInfo->getXLen() == 32) { in selectRISCVMultilib()
/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DRISCV.cpp1074 mergedXlen = info.getXLen(); in mergeArch()
/freebsd/contrib/llvm-project/clang/lib/Driver/
H A DDriver.cpp691 unsigned XLen = (*ISAInfo)->getXLen(); in computeTargetTriple()