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Searched refs:getVectorMinNumElements (Results 1 – 20 of 20) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/
H A DMachineValueType.h243 unsigned NElts = getVectorMinNumElements(); in isPow2VectorType()
278 unsigned getVectorMinNumElements() const { in getVectorMinNumElements() function
292 return ElementCount::get(getVectorMinNumElements(), isScalableVector()); in getVectorElementCount()
301 return getVectorMinNumElements(); in getVectorNumElements()
/freebsd/contrib/llvm-project/llvm/lib/CodeGenTypes/
H A DLowLevelType.cpp21 bool asVector = VT.getVectorMinNumElements() > 1 || VT.isScalableVector(); in LLT()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h354 unsigned getVectorMinNumElements() const { in getVectorMinNumElements() function
466 unsigned NElts = getVectorMinNumElements(); in isPow2VectorType()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1658 DAG.getVectorIdxConstant(IdxVal + LoVT.getVectorMinNumElements(), dl)); in SplitVecRes_EXTRACT_SUBVECTOR()
1672 unsigned VecElems = VecVT.getVectorMinNumElements(); in SplitVecRes_INSERT_SUBVECTOR()
1673 unsigned SubElems = SubVecVT.getVectorMinNumElements(); in SplitVecRes_INSERT_SUBVECTOR()
1674 unsigned LoElems = LoVT.getVectorMinNumElements(); in SplitVecRes_INSERT_SUBVECTOR()
1991 unsigned LoNumElts = Lo.getValueType().getVectorMinNumElements(); in SplitVecRes_INSERT_VECTOR_ELT()
2071 DAG.getVScale(dl, EltVT, StepVal * LoVT.getVectorMinNumElements()); in SplitVecRes_STEP_VECTOR()
2502 while (CheckVT.getVectorMinNumElements() > 1) { in SplitVecRes_VECTOR_COMPRESS()
3284 DAG.getVectorIdxConstant(LoVT.getVectorMinNumElements(), DL)); in SplitVecRes_VP_SPLICE()
3782 uint64_t LoElts = Lo.getValueType().getVectorMinNumElements(); in SplitVecOp_INSERT_SUBVECTOR()
3802 uint64_t LoEltsMin = Lo.getValueType().getVectorMinNumElements(); in SplitVecOp_EXTRACT_SUBVECTOR()
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H A DSelectionDAG.cpp3445 if (!isUIntN(BitWidth, Op.getValueType().getVectorMinNumElements())) in computeKnownBits()
3448 APInt(BitWidth, Op.getValueType().getVectorMinNumElements()); in computeKnownBits()
5655 return KnownIdx.getMaxValue().uge(VecVT.getVectorMinNumElements()); in canCreateUndefOrPoison()
6219 unsigned IdentityIndex = i * Op.getValueType().getVectorMinNumElements(); in foldCONCAT_VECTORS()
6539 assert(VT.getVectorMinNumElements() < in getNode()
6540 N1.getValueType().getVectorMinNumElements() && in getNode()
7812 VT.getVectorMinNumElements() <= N1VT.getVectorMinNumElements()) && in getNode()
7816 (VT.getVectorMinNumElements() + N2C->getZExtValue()) <= in getNode()
7817 N1VT.getVectorMinNumElements()) && in getNode()
7835 unsigned Factor = VT.getVectorMinNumElements(); in getNode()
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H A DDAGCombiner.cpp18264 NumElts = VT.getVectorMinNumElements(); in combineRepeatedFPDivisors()
25401 N->getOperand(0).getValueType().getVectorMinNumElements(); in visitCONCAT_VECTORS()
25449 (Index % SubVT.getVectorMinNumElements()) == 0) { in getSubVectorSrc()
25450 uint64_t SubIdx = Index / SubVT.getVectorMinNumElements(); in getSubVectorSrc()
25632 unsigned NumElts = VT.getVectorMinNumElements(); in narrowExtractedVectorLoad()
25635 if (Index == 0 && NumElts >= Ld->getValueType(0).getVectorMinNumElements()) in narrowExtractedVectorLoad()
25854 unsigned NumInsElts = InsSubVT.getVectorMinNumElements(); in visitEXTRACT_SUBVECTOR()
25856 unsigned NumSubElts = NVT.getVectorMinNumElements(); in visitEXTRACT_SUBVECTOR()
25872 unsigned SrcNumElts = SrcVT.getVectorMinNumElements(); in visitEXTRACT_SUBVECTOR()
25873 unsigned DestNumElts = V.getValueType().getVectorMinNumElements(); in visitEXTRACT_SUBVECTOR()
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H A DLegalizeIntegerTypes.cpp5986 unsigned NElts = NInVT.getVectorMinNumElements(); in PromoteIntRes_EXTRACT_SUBVECTOR()
6165 unsigned NumOutElem = NOutVT.getVectorMinNumElements(); in PromoteIntRes_CONCAT_VECTORS()
6398 unsigned OpNumElts = Op.getValueType().getVectorMinNumElements(); in PromoteIntOp_CONCAT_VECTORS()
H A DSelectionDAGBuilder.cpp816 unsigned IntermediateNumElts = IntermediateVT.getVectorMinNumElements(); in getCopyToPartsVector()
12569 unsigned NumElts = VT.getVectorMinNumElements(); in visitVectorReverse()
12586 unsigned OutNumElts = OutVT.getVectorMinNumElements(); in visitVectorDeinterleave()
12629 unsigned NumElts = InVT.getVectorMinNumElements(); in visitVectorInterleave()
H A DTargetLowering.cpp10602 unsigned NElts = VecVT.getVectorMinNumElements(); in clampDynamicVectorIndex()
11907 if (TrailingElts > VT.getVectorMinNumElements()) { in expandVectorSplice()
12055 unsigned Stride = AccVT.getVectorMinNumElements(); in expandPartialReduceMLA()
12056 unsigned ScaleFactor = MulOpVT.getVectorMinNumElements() / Stride; in expandPartialReduceMLA()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp86 unsigned VL = VT.getVectorMinNumElements(); in getRISCVInstructionCost()
93 unsigned VL = VT.getVectorMinNumElements(); in getRISCVInstructionCost()
907 ContainerVT.getVectorMinNumElements() / M1VT.getVectorMinNumElements(); in getShuffleCost()
2306 ((Index == -1U) || (Index >= LT.second.getVectorMinNumElements() && in getVectorInstrCost()
H A DRISCVISelLowering.cpp185 if (VT.getVectorMinNumElements() < MinElts) in RISCVTargetLowering()
3718 if (!CIdx || CIdx->getZExtValue() >= VT.getVectorMinNumElements()) in matchSplatAsGather()
3734 if (SrcContainerVT.getVectorMinNumElements() < in matchSplatAsGather()
3735 ContainerVT.getVectorMinNumElements()) in matchSplatAsGather()
4368 unsigned NumOpElts = M1VT.getVectorMinNumElements(); in lowerBUILD_VECTOR()
4703 V2.getConstantOperandVal(1) != VT.getVectorMinNumElements()) in foldConcatVector()
5429 unsigned NumOpElts = M1VT.getVectorMinNumElements(); in lowerShuffleViaVRegSplitting()
5430 unsigned NumElts = ContainerVT.getVectorMinNumElements(); in lowerShuffleViaVRegSplitting()
6203 ContainerVT.getVectorMinNumElements() / M1VT.getVectorMinNumElements(); in lowerVECTOR_SHUFFLE()
6213 unsigned SubIdx = M1VT.getVectorMinNumElements() * i; in lowerVECTOR_SHUFFLE()
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H A DRISCVISelDAGToDAG.cpp366 assert(ContainedTyNumElts == IndexVT.getVectorMinNumElements() && in selectVLXSEG()
439 assert(ContainedTyNumElts == IndexVT.getVectorMinNumElements() && in selectVSXSEG()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenDAGPatterns.cpp665 return B.getVectorMinNumElements() < P.getVectorMinNumElements(); in EnforceVectorSubVectorTypeIs()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp221 switch (VT.getVectorMinNumElements()) { in getPromotedVTForPredicate()
2146 if (ResVT.getVectorMinNumElements() == 1 || in shouldExpandGetActiveLaneMask()
5558 unsigned ElementSize = 128 / N->getValueType(0).getVectorMinNumElements(); in optimizeIncrementingWhile()
6402 return DataVT.isFixedLengthVector() || DataVT.getVectorMinNumElements() > 2; in shouldRemoveExtendFromGSIndex()
11510 unsigned BlockSize = AArch64::SVEBitsPerBlock / Ty.getVectorMinNumElements(); in LowerVECTOR_SPLICE()
14493 unsigned NumElts = N.getValueType().getVectorMinNumElements(); in isAllActivePredicate()
14500 if (N.getValueType().getVectorMinNumElements() < NumElts) in isAllActivePredicate()
14512 return N.getValueType().getVectorMinNumElements() >= NumElts; in isAllActivePredicate()
15478 unsigned NumElts = VT.getVectorMinNumElements(); in LowerINSERT_SUBVECTOR()
15529 assert(Idx == InVT.getVectorMinNumElements() && in LowerINSERT_SUBVECTOR()
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H A DAArch64TargetTransformInfo.cpp2986 DstTyL.first * DstTyL.second.getVectorMinNumElements(); in isWideningInstruction()
2988 SrcTyL.first * SrcTyL.second.getVectorMinNumElements(); in isWideningInstruction()
H A DAArch64ISelDAGToDAG.cpp1831 unsigned Key = VT.getVectorMinNumElements(); in SelectOpcodeFromVT()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp1055 unsigned Index = NarrowVT.getVectorMinNumElements(); in PreprocessISelDAG()
1083 unsigned Index = NarrowVT.getVectorMinNumElements(); in PreprocessISelDAG()
H A DX86ISelLowering.cpp45364 *DAG.getContext(), LowerOp.getValueType().getVectorMinNumElements()); in combineBitcastvxi1()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp2228 unsigned VecLen = VT.getVectorMinNumElements(); in getPreferredVectorAction()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp17213 128 / AVT.getVectorMinNumElements())), in PerformVECREDUCE_ADDCombine()