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Searched refs:getVGPRClassForBitWidth (Results 1 – 4 of 4) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h185 const TargetRegisterClass *getVGPRClassForBitWidth(unsigned BitWidth) const;
H A DSIRegisterInfo.cpp2676 SIRegisterInfo::getVGPRClassForBitWidth(unsigned BitWidth) const { in getVGPRClassForBitWidth() function in SIRegisterInfo
2883 const TargetRegisterClass *VRC = getVGPRClassForBitWidth(Size); in getEquivalentVGPRClass()
3098 return getVGPRClassForBitWidth( in getRegClassForSizeOnBank()
3231 return RC.hasSuperClassEq(getVGPRClassForBitWidth(getRegSizeInBits(RC))); in isProperlyAlignedRC()
H A DSIISelLowering.cpp104 addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96)); in SITargetLowering()
110 addRegisterClass(MVT::v4f32, TRI->getVGPRClassForBitWidth(128)); in SITargetLowering()
113 addRegisterClass(MVT::v5f32, TRI->getVGPRClassForBitWidth(160)); in SITargetLowering()
116 addRegisterClass(MVT::v6f32, TRI->getVGPRClassForBitWidth(192)); in SITargetLowering()
119 addRegisterClass(MVT::v3f64, TRI->getVGPRClassForBitWidth(192)); in SITargetLowering()
122 addRegisterClass(MVT::v7f32, TRI->getVGPRClassForBitWidth(224)); in SITargetLowering()
125 addRegisterClass(MVT::v8f32, TRI->getVGPRClassForBitWidth(256)); in SITargetLowering()
128 addRegisterClass(MVT::v4f64, TRI->getVGPRClassForBitWidth(256)); in SITargetLowering()
131 addRegisterClass(MVT::v9f32, TRI->getVGPRClassForBitWidth(288)); in SITargetLowering()
134 addRegisterClass(MVT::v10f32, TRI->getVGPRClassForBitWidth(320)); in SITargetLowering()
[all …]
H A DSILoadStoreOptimizer.cpp1878 : TRI->getVGPRClassForBitWidth(BitWidth); in getTargetRegisterClass()